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參數(shù)資料
| 型號： | M38049FFSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 75/135頁 |
| 文件大小： | 2055K |
| 代理商： | M38049FFSP |
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75
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 69 Interrupt request signal generating timing
Fig. 68 Structure of I
2
C status register
Bit 6: Communication mode specification bit (transfer direc-
tion specification bit: TRX)
This bit decides a direction of transfer for data communication.
When this bit is
“
0,
”
the reception mode is selected and the data of
a transmitting device is received. When the bit is
“
1,
”
the transmis-
sion mode is selected and address data and control data are
output onto the SDA in synchronization with the clock generated
on the SCL.
This bit is set/reset by software and hardware. About set/reset by
hardware is described below. This bit is set to
“
1
”
by hardware
when all the following conditions are satisfied:
When ALS is
“
0
”
In the slave reception mode or the slave transmission mode
When the R/W bit reception is
“
1
”
This bit is set to
“
0
”
in one of the following conditions:
When arbitration lost is detected.
When a STOP condition is detected.
When writing
“
1
”
to this bit by software is invalid by the START
condition duplication preventing function
(Note)
.
With MST =
“
0
”
and when a START condition is detected.
With MST =
“
0
”
and when ACK non-return is detected.
At reset
Bit 7: Communication mode specification bit (master/slave
specification bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is
“
0,
”
the slave is specified, so that a START
condition and a STOP condition generated by the master are re-
ceived, and data communication is performed in synchronization
with the clock generated by the master. When this bit is
“
1,
”
the
master is specified and a START condition and a STOP condition
are generated. Additionally, the clocks required for data communi-
cation are generated on the SCL.
This bit is set to
“
0
”
in one of the following conditions.
Immediately after completion of the byte which has lost arbitra-
tion when arbitration lost is detected
When a STOP condition is detected.
Writing
“
1
”
to this bit by software is invalid by the START condi-
tion duplication preventing function
(Note)
.
At reset
Note:
START condition duplication preventing function
The MST, TRX, and BB bits is set to
“
1
”
at the same time after con-
firming that the BB flag is
“
0
”
in the procedure of a START condition
occurrence. However, when a START condition by another master
device occurs and the BB flag is set to
“
1
”
immediately after the con-
tents of the BB flag is confirmed, the START condition duplication
preventing function makes the writing to the MST and TRX bits in-
valid. The duplication preventing function becomes valid from the
rising of the BB flag to reception completion of slave address.
b
7
M
S
T
b
0
I
2
C
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1
3
1
6
)
Last receive bit
(Note)
0 : Last bit =
“
0
”
1 : Last bit =
“
1
”
e
n
e
r
a
l
c
a
l
(
N
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)
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:
:
)
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a
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d
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(
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N
: N
: D
t
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e
d
e
c
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e
d
c
t
e
d
t
S
C
L
p
0
1
i
n
:
:
S
S
l
o
C
C
w
h
p
p
o
i
i
l
n
n
d
l
l
b
o
o
i
w
w
t
L
L
h
r
o
e
l
e
d
s
e
l
a
B
u
s
:
:
b
B
B
u
s
u
u
y
s
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f
f
b
l
a
e
u
g
e
s
y
0
1
r
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
TRX B
B P
I
N A
L A
A
S A
D
0 L
R
B
Note:
These bits and flags can be read out, but cannot be written.
Write
“
0
”
to these bits at writing.
SCL
PIN
I
2
C
I
R
Q
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