參數(shù)資料
型號： M38037M6-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 56/135頁
文件大?。?/td> 2055K
代理商： M38037M6-XXXFP
56
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Serial I/O2
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
[Serial I/O2 Control Register (SIO2CON)]
001D
16
The serial I/O2 control register contains eight bits which control
various serial I/O2 functions.
Fig. 45 Structure of serial I/O2 control register
Fig. 46 Block diagram of serial I/O2
Serial I/O2 control register
(SIO2CON : address 001D
16
)
b
7
Internal synchronous clock selection bits
b
0 0 0: f(X
IN
)/8 (f(X
CIN
)/8 in low-speed mode)
0 0 1: f(X
IN
)/16 (f(X
CIN
)/16 in low-speed mode)
0 1 0: f(X
IN
)/32 (f(X
CIN
)/32 in low-speed mode)
0 1 1: f(X
IN
)/64 (f(X
CIN
)/64 in low-speed mode)
1 1 0: f(X
IN
)/128 (f(X
CIN
)/128 in low-speed mode)
1 1 1: f(X
IN
)/256 (f(X
CIN
)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
1: S
OUT2
,S
CLK2
signal output
S
RDY2
output enable bit
0: I/O port
1: S
RDY2
signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P5
/S
P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
b
0
2
“
1
”
“
0
”
“
0
”
“
1
t
”
e
“
0
”
“
1
s
”
S
R
D
Y
2
S
C
L
K
2
“
0
”
“
1
u
”
t
1/8
1/16
1/32
1/64
1/128
1/256
Data bus
Serial I/O2
interrupt request
S
e
r
i
a
l
I
/
O
2
p
o
r
t
e
l
e
c
t
i
o
n
b
i
t
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
S
c
y
i
n
c
c
u
h
i
t
r
o
n
i
z
a
t
i
o
n
r
S
e
r
i
a
l
I
/
O
2
p
o
r
s
l
e
c
t
i
o
n
b
i
t
Serial I/O2 synchronous
clock selection bit
S
R
D
Y
2
o
p
u
t
e
n
a
b
l
e
b
i
t
External clock
In
c
t
o
e
c
r
k
n
a
s
l
e
s
l
e
y
n
c
c
i
o
h
n
r
o
b
n
i
o
t
s
u
s
l
t
D
i
v
i
e
r
P
5
2
/
S
C
L
K
2
P
5
1
/
S
O
U
T
2
P
5
0
/
S
I
N
2
P
5
2
l
a
t
c
h
P5
1
latch
P
5
3
l
a
t
c
h
P
5
3
/
S
R
D
Y
2
f
(
X
I
N
)
(f(X
CIN
) in low-speed mode)
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