參數(shù)資料
型號： M38037M6-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 15/135頁
文件大小： 2055K
代理商： M38037M6-XXXFP
15
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
MISRG
(1) Bit 0 of address 0010
16:
Oscillation stabilizing time set af-
ter STP instruction released bit
When the MCU stops the clock oscillation by the STP instruction
and the STP instruction has been released by an external interrupt
source, usually, the fixed values of Timer 1 and Prescaler 12
(Timer 1 = 01
16
, Prescaler 12 = FF
16
) are automatically reloaded
in order for the oscillation to stabilize. The user can inhibit the au-
tomatic setting by setting “1” to bit 0 of MISRG (address 0010
16
).
However, by setting this bit to “1”, the previous values, set just be-
fore the STP instruction was executed, will remain in Timer 1 and
Prescaler 12. Therefore, you will need to set an appropriate value
to each register, in accordance with the oscillation stabilizing time,
before executing the STP instruction.
Figure 12 shows the structure of MISRG.
(2) Bits 1, 2, 3 of address 0010
16:
Middle-speed Mode Auto-
matic Switch Function
In order to switch the clock mode of an MCU which has a sub-
clock, the following procedure is necessary:
set CPU mode register (003B
16
) --> start main clock oscillation -->
wait for oscillation stabilization --> switch to middle-speed mode
(or high-speed mode).
However, the 3803/3804 group has the built-in function which au-
tomatically switches from low to middle-speed mode either by the
SCL/SDA interrupt (only for the 3804 group) or by program.
G
Middle-speed mode automatic switch by SCL/SDA Interrupt
(only for 3804 group)
The SCL/SDA interrupt source enables an automatic switch when
the middle-speed mode automatic switch set bit (bit 1) of MISRG
(address 0010
16
) is set to “1”. The conditions for an automatic
switch execution depend on the settings of bits 5 and 6 of the I
2
C
start/stop condition control register (address 0016
16
). Bit 5 is the
SCL/SDA interrupt pin polarity selection bit and bit 6 is the SCL/
SDA interrupt pin selection bit. The main clock oscillation stabiliz-
ing time can also be selected by middle-speed mode automatic
switch wait time set bit (bit 2) of the MISRG.
G
Middle-speed mode automatic switch by program(for 3804/
3803 group)
The middle-speed mode can also be automatically switched by
program while operating in low-speed mode. By setting the
middle-speed automatic switch start bit (bit 3) of MISRG (address
0010
16
) to “1” in the condition that the middle-speed mode auto-
matic switch set bit is “1” while operating in low-speed mode, the
MCU will automatically switch to middle-speed mode. In this case,
the oscillation stabilizing time of the main clock can be selected by
the middle-speed automatic switch wait time set bit (bit 2) of
MISRG (address 0010
16
).
Fig.12 Structure of MISRG
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