參數(shù)資料
型號(hào)： M38037M6-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 42/135頁
文件大小： 2055K
代理商： M38037M6-XXXFP
42
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
G
16-bit Timers
The timer Z is a 16-bit timer. When the timer reaches
“
0000
16
”
, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When the timer underflows, the interrupt request bit corresponding
to the timer Z is set to
“
1
”
.
Read and write operation to a 16-bit timer must be performed for
both high- and low-order bytes. When reading a 16-bit timer, read
from the high-order byte first, followed by the low-order byte.
When writing to a 16-bit timer, write to the low-order byte first, fol-
lowed by the high-order byte. The 16-bit timer cannot perform the
correct operation when reading during write operation, or when
writing during read operation.
The timer Z can select the count source by the timer Z count
source selection bits of timer Y, Z count source selection register
(bits 7 to 4 at address 000F
16
).
Timer Z can select one of seven operating modes by setting the
timer Z mode register (address 002A
16
).
(1) Timer mode
G
Mode selection
This mode can be selected by setting
“
000
”
to the timer Z operat-
ing mode bits (bits 2 to 0) and setting
“
0
”
to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A
16
).
G
Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(X
IN
); or f(X
CIN
) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(X
CIN
); or f(X
CIN
) can be selected as the count
source.
G
Interrupt
When an underflow occurs, the INT
0
/timer Z interrupt request bit
(bit 0) of the interrupt request register 1 (address 003C
16
) is set to
“
1
”
.
G
Explanation of operation
During timer stop, usually write data to a latch and a timer at the
same time to set the timer value.
The timer count operation is started by setting
“
0
”
to the timer Z
count stop bit (bit 6) of the timer Z mode register (address
002A
16
).
When the timer reaches
“
0000
16
”
, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
When writing data to the timer during operation, the data is written
only into the latch. Then the new latch value is reloaded into the
timer at the next underflow.
(2) Event counter mode
G
Mode selection
This mode can be selected by setting
“
000
”
to the timer Z operat-
ing mode bits (bits 2 to 0) and setting
“
1
”
to the timer/event
counter mode switch bit (bit 7) of the timer Z mode register (ad-
dress 002A
16
).
The valid edge for the count operation depends on the CNTR
2
ac-
tive edge switch bit (bit 5) of the timer Z mode register (address
002A
16
). When it is
“
0
”
, the rising edge is valid. When it is
“
1
”
, the
falling edge is valid.
G
Interrupt
The interrupt at an underflow is the same as the timer mode
’
s.
G
Explanation of operation
The operation is the same as the timer mode
’
s.
Set the double-function port of CNTR
2
pin and port P4
7
to input in
this mode.
Figure 34 shows the timing chart of the timer/event counter mode.
(3) Pulse output mode
G
Mode selection
This mode can be selected by setting
“
001
”
to the timer Z operat-
ing mode bits (bits 2 to 0) and setting
“
0
”
to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A
16
).
G
Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(X
IN
); or f(X
CIN
) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(X
CIN
); or f(X
CIN
) can be selected as the count
source.
G
Interrupt
The interrupt at an underflow is the same as the timer mode
’
s.
G
Explanation of operation
The operation is the same as the timer mode
’
s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR
2
pin. When the CNTR
2
active edge switch bit (bit 5) of
the timer Z mode register (address 002A
16
) is
“
0
”
, the output starts
with
“
H
”
level. When it is
“
1
”
, the output starts with
“
L
”
level.
I
Precautions
Set the double-function port of CNTR
2
pin and port P4
7
to output
in this mode.
[During timer operation stop]
The output from CNTR
2
pin is initialized to the level depending on
CNTR
2
active edge switch bit by writing to the timer.
[During timer operation enabled]
When the value of the CNTR
2
active edge switch bit is changed,
the output level of CNTR
2
pin is inverted.
Figure 35 shows the timing chart of the pulse output mode.
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