參數(shù)資料
型號(hào): M37531RSS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 8 MHz, MICROCONTROLLER, CDIP42
封裝: SHRINK, CERAMIC, PIGGY BACK, DIP-42
文件頁數(shù): 43/76頁
文件大?。?/td> 1022K
代理商: M37531RSS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7531 Group
MITSUBISHI MICROCOMPUTERS
48
Timing Requirements (Extended operating temperature version)
Table 20 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(SCLK–SDATA)
th(SCLK–SDATA)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0 input “H” pulse width
CNTR0, INT0 input “L” pulse width
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
2
125
50
200
80
1000
400
200
s
ns
Table 21 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Max.
Symbol
Parameter
Unit
Min.
Typ.
Limits
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(SCLK–SDATA)
th(SCLK–SDATA)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0 input “H” pulse width
CNTR0, INT0 input “L” pulse width
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
2
250
100
500
230
2000
950
400
s
ns
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