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參數(shù)資料
| 型號： | M37531RSS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 8 MHz, MICROCONTROLLER, CDIP42 |
| 封裝： | SHRINK, CERAMIC, PIGGY BACK, DIP-42 |
| 文件頁數(shù)： | 27/76頁 |
| 文件大?。?/td> | 1022K |
| 代理商： | M37531RSS |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7531 Group
MITSUBISHI MICROCOMPUTERS
33
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the T flag and the D flag because of their
effect on calculations.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the pre-
vious contents. For executing the instruction for the changed con-
tents, execute one instruction before executing the BBC or BBS in-
struction.
Decimal Calculations
For calculations in decimal notation, set the decimal mode flag D to
“1”, then execute the ADC instruction or SBC instruction. In this
case, execute SEC instruction, CLC instruction or CLD instruction
after executing one instruction before the ADC instruction or SBC
instruction.
In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
Timers
When n (0 to 255) is written to a timer latch, the frequency division
ratio is 1/(n+1).
When a count source of timer X is switched, stop a count of timer X.
Ports
The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory opera-
tion instruction when the T flag is “1”, addressing mode using di-
rection register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA in-
struction, etc.
Set "1" to each bit 6 of the port P3 direction register and the port P3
register.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Make sure that f(XIN) is 500kHz or more during A-D conversion.
Do not execute the STP instruction during A-D conversion.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock
φ by the number of cycles mentioned
in the machine-language instruction table.
The frequency of the internal clock
φ is the same as that of the XIN in
double-speed mode, twice the XIN cycle in high-speed mode and 8
times the XIN cycle in middle-speed mode.
CPU Mode Register
The oscillation mode selection bit can be rewritten only once after
releasing reset. However, after rewriting it is disable to write any value
to the bit.
When a ceramic oscillation is selected, a double-speed mode of the
clock division ratio selection bits can be used. Do not use it when a
CR oscillation is selected.
NOTES ON USE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable
for high frequencies as bypass capacitor between power source pin
(Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to
as close as possible. For bypass capacitor which should not be lo-
cated too far from the pins to be connected, a ceramic capacitor of
0.01 F to 0.1 F is recommended.
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block by a
low-ohmic resistance, since it has the multiplexed function to be a
programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss pin
and Vss pin with 1 to 10 k
resistance.
The mask ROM version track of CNVss pin has no operational inter-
ference even if it is connected via a resistor.
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