
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
83
MULTI-MASTER I
2
C-BUS BUS LINE CHARACTERISTICS
Bus free time
Hold time for START condition
“L” period of SCL clock
Rising time of both SCL and SDA signals
Data hold time
“H” period of SCL clock
Falling time of both SCL and SDA signals
Data set-up time
Set-up time for repeated START condition
Set-up time for STOP condition
t
BUF
t
HD:STA
t
LOW
t
R
t
HD:DAT
t
HIGH
t
F
t
SU:DAT
t
SU:STA
t
SU:STO
Min.
4.7
4.0
4.7
0
4.0
250
4.7
4.0
Max.
1000
300
Min.
1.3
0.6
1.3
20+0.1C
b
0
0.6
20+0.1C
b
100
0.6
0.6
Max.
300
0.9
300
μ
s
μ
s
μ
s
ns
μ
s
μ
s
ns
ns
μ
s
μ
s
Unit
Standard clock mode High-speed clock mode
Parameter
Symbol
Note:
C
b
= total capacitance of 1 bus line
Fig. 83. Definition diagram of timing on multi-master I
2
C-BUS
Resolution
Absolute accuracy
Max.
6
±
2
bits
LSB
Min.
0
Limits
Typ.
Unit
Test conditions
Parameter
Symbol
—
—
±
1
Note:
When Vcc = 5 V, 1 LSB = 5/64 V.
A-D COMPARATOR CHARACTERISTICS
(V
CC
= 5 V
±
10 %, V
SS
= 0 V, f(X
IN
) = 8 MHz, T
a
= –10
°
C to 70
°
C, unless otherwise noted)
SDA
SCL
P
t
BUF
S
t
HD
:
STA
t
LOW
t
R
t
HD
:
DAT
t
HIGH
t
F
t
SU
:
DAT
t
SU
:
STA
Sr
P
t
SU
:
STO
t
HD
:
STA
S
Sr
P
: Start condition
: Restart condition
: Stop condition