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參數(shù)資料
| 型號(hào)： | M3720 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1 KEY 1 SOUND |
| 中文描述： | 1鍵1聲 |
| 文件頁(yè)數(shù)： | 37/121頁(yè) |
| 文件大?。?/td> | 1907K |
| 代理商： | M3720 |
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37
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
(10) Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
I
2
C control register (address 00DC
16
) to “0.” The first 7-bit ad-
dress data transmitted from the master is compared with the high-
order 7-bit slave address stored in the I
2
C address register (ad-
dress 00DA
16
). At the time of this comparison, address compari-
son of the RBW bit of the I
2
C address register (address 00DA
16
)
is not made. For the data transmission format when the 7-bit ad-
dressing format is selected, refer to Figure 34, (1) and (2).
10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I
2
C control register (address 00DC
16
) to “1.” An address compari-
son is made between the first-byte address data transmitted from
the master and the 7-bit slave address stored in the I
2
C address
register (address 00DA
16
). At the time of this comparison, an ad-
dress comparison between the RBW bit of the I
2
C address regis-
ter (address 00DA
16
) and the R/W bit which is the last bit of the
address data transmitted from the master is made. In the 10-bit
addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
When the first-byte address data matches the slave address, the
AAS bit of the I
2
C status register (address 00DB
16
) is set to “1.” After
the second-byte address data is stored into the I
2
C data shift register
(address 00D9
16
), make an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd bytes matches the slave address, set the RBW bit of
the I
2
C address register (address 00DA
16
) to “1” by software. This
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I
2
C address register (address 00DA
16
). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 34, (3) and (4).
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
Set a slave address in the high-order 7 bits of the I
2
C address
register (address 00DA
16
) and “0” in the RBW bit.
Set the ACK return mode and SCL = 100 kHz by setting “85
16
” in
the I
2
C clock control register (address 00DD
16
).
Set “10
16
” in the I
2
C status register (address 00DB
16
) and hold
the SCL at the HIGH.
Set a communication enable status by setting “48
16
” in the I
2
C
control register (address 00DC
16
).
Set the address data of the destination of transmission in the high-
order 7 bits of the I
2
C data shift register (address 00D9
16
) and set
“0” in the least significant bit.
Set “F0
16
” in the I
2
C status register (address 00DB
16
) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
Set transmit data in the I
2
C data shift register (address 00D9
16
).
At this time, an SCL and an ACK clock automatically occurs.
When transmitting control data of more than 1 byte, repeat step
.
Set “D0
16
” in the I
2
C status register (address 00DB
16
). After this,
if ACK is not returned or transmission ends, a STOP condition will
be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
Set a slave address in the high-order 7 bits of the I
2
C address
register (address 00DA
16
) and “0” in the RBW bit.
Set the no ACK clock mode and SCL = 400 kHz by setting “25
16
”
in the I
2
C clock control register (address 00DD
16
).
Set “10
16
” in the I
2
C status register (address 00DB
16
) and hold
the SCL at the HIGH.
Set a communication enable status by setting “48
16
” in the I
2
C
control register (address 00DC
16
).
When a START condition is received, an address comparison is
made.
When all transmitted addresses are “0” (general call) :
AD0 of the I
2
C status register (address 00DB
16
) is set to “1” and
an interrupt request signal occurs.
When the transmitted addresses match the address set in :
AAS of the I
2
C status register (address 00DB
16
) is set to “1” and
an interrupt request signal occurs.
In the cases other than the above :
AD0 and AAS of the I
2
C status register (address 00DB
16
) are
set to “0” and no interrupt request signal occurs.
Set dummy data in the I
2
C data shift register (address 00D9
16
).
When receiving control data of more than 1 byte, repeat step
When a STOP condition is detected, the communication ends.
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M3720-1 | 1 KEY 1 SOUND |
| M3720-10 | 1 KEY 1 SOUND |
| M3720-2 | 1 KEY 1 SOUND |
| M3720-3 | 1 KEY 1 SOUND |
| M3720-4 | 1 KEY 1 SOUND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3720-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
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