
32
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
(4) I
2
C Control Register
The I
2
C control register (address 00DC
16
) controls the data commu-
nication format.
I
Bits 0 to 2: Bit Counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “000
2
” and
the address data is always transmitted and received in 8 bits.
I
Bit 3: I
2
C Interface Use Enable Bit (ESO)
This bit enables usage of the multimaster I
2
C BUS interface. When
this bit is set to “0,” the use disable status is provided, so the SDA
and the SCL become high-impedance. When the bit is set to “1,” use
of the interface is enabled.
When ESO = “0,” the following is performed.
PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I
2
C
status register at address 00F8
16
).
Writing data to the I
2
C data shift register (address 00F6
16
) is dis-
abled.
I
Bit 4: Data Format Selection Bit (ALS)
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
eral call (refer to “(5) I
2
C Status Register,” bit 1) is received, trans-
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
Fig. 28. I
2
C Control Register
I
Bit 5: Addressing Format Selection Bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
the high-order 7 bits (slave address) of the I
2
C address register (ad-
dress 00F7
16
) are compared with address data. When this bit is set
to “1,” the 10-bit addressing format is selected, all the bits of the I
2
C
address register are compared with address data.
I
Bits 6 and 7: Connection Control Bits between I
2
C-BUS Interface
and Ports (BSEL0, BSEL1)
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 28).
Fig. 27. Connection Port Control by BSEL0 and BSEL1
“0”
“1” BSEL0
“0”
“1” BSEL1
SCL1/P4
5
SCL2/P4
3
Multi-master
2
C-BUS
I
SCL
SDA
SCL3/P4
1
“0”
“1”
CIIC (Note 2)
“0”
“1” BSEL0
“0”
“1” BSEL1
SDA1/P4
4
SDA2/P4
2
SDA3/P4
0
“0”
“1”
CIIC (Note 2)
Notes 1 :
When using multi-master I
2
C-BUS interface, set bits 3 to
7 of the serial I/O mode register (address 00DE
16
) to “1.”
2 :
CIIC is bit 2 of the serial I/O control register (address
0207
16
) (refer to Figure 21).
b7 b6 b5 b4 b3 b2 b1 b0
0
to
2
Bit counter
(Number of transmit/recieve
bits)
(BC0 to BC2)
b2 b1 b0
0 0 0 : 8
0 0 1 : 7
0 1 0 : 6
0 1 1 : 5
1 0 0 : 4
1 0 1 : 3
1 1 0 : 2
1 1 1 : 1
3
I
2
C-BUS interface use
enable bit (ESO)
0 : Disabled
1 : Enabled
4
Data format selection bit
(ALS)
0 : Addressing mode
1 : Free data format
5
Addressing format selection
bit (10BIT SAD)
0 : 7-bit addressing format
1 : 10-bit addressing format
6, 7 Connection control bits
between I C-BUS interface
and ports
b7 b6 Connection port (See note)
0 0 : None
0 1 : SCL1, SDA1
1 0 : SCL2, SDA2
1 1 : SCL1, SDA1
SCL2, SDA2
0
0
0
0
0
I
2
C control register (S1D : address 00DC
16
)
I
2
C Control Register
B
Name
Functions
After reset
R W
Note:
When using ports P1
1
-P1
4
as I C-BUS interface, the output structure changes
automatically from CMOS output to N-channel open-drain output.
R W
R W
R W
R W
R W