參數(shù)資料
型號(hào): M3720
廠(chǎng)商: Electronic Theatre Controls, Inc.
英文描述: 1 KEY 1 SOUND
中文描述: 1鍵1聲
文件頁(yè)數(shù): 17/121頁(yè)
文件大?。?/td> 1907K
代理商: M3720
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
17
INTERRUPTS
Interrupts can be caused by 15 different sources consisting of 3 ex-
ternal, 10 internal, 1 software, and reset. Interrupts are vectored in-
terrupts with priorities as shown in Table 1. Reset is also included in
the table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 10 to 13 show the inter-
rupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 9 shows interrupt control.
Interrupt Causes
(1) V
SYNC
and CRT interrupts
The V
SYNC
interrupt is an interrupt request synchronized with
the vertical sync signal.
The CRT interrupt occurs after character block display to the CRT
is completed.
(2) INT1, INT2 interrupts
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3 and 4 of the interrupt interval determination control register
(address 00D8
16
) : when this bit is “0,” a change from “L” to “H” is
detected; when it is “1,” a change from “H” to “L” is detected.
Note that all bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial
I/O function.
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vector Addresses
FFFF
16
, FFFE
16
FFFD
16
, FFFC
16
FFFB
16
, FFFA
16
FFF9
16
, FFF8
16
FFF7
16
, FFF6
16
FFF5
16
, FFF4
16
FFF3
16
, FFF2
16
FFF1
16
, FFF0
16
FFEF
16
, FFEE
16
FFED
16
, FFEC
16
FFEB
16
, FFEA
16
FFE7
16
, FFE6
16
FFE3
16
, FFE2
16
FFDF
16
, FFDE
16
Interrupt Source
Reset
CRT interrupt
INT1 interrupt
INT2 interrupt
Timer 4 interrupt
f(X
IN
)/4096 interrupt
V
SYNC
interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
Serial I/O interrupt
Multi-master I
2
C-BUS interface interrupt
Timer 5 · 6 interrupt
BRK instruction interrupt
Note :
Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Source switch by software (See note)
Non-maskable (software interrupt)
Table 1. Interrupt Vector Addresses and Priority
相關(guān)PDF資料
PDF描述
M3720-1 1 KEY 1 SOUND
M3720-10 1 KEY 1 SOUND
M3720-2 1 KEY 1 SOUND
M3720-3 1 KEY 1 SOUND
M3720-4 1 KEY 1 SOUND
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M3720-1 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:1 KEY 1 SOUND
M3720-10 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:1 KEY 1 SOUND
M3720-2 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:1 KEY 1 SOUND
M3720-3 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:1 KEY 1 SOUND
M3720-4 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:1 KEY 1 SOUND