
M36W216TI, M36W216BI
4/62
FLASH STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. .. .. . . ... .. . . . . . ... .29
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... ... 29
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . .... . . . ... . . . . . . .. ... .. .. ... .. .. .... 29
Erase Status (Bit 5) . . . . . . . . . . . . ... .. . ... . . .. .. ... .... .. .. .. . . . . ... .. . ... . . . ..29
Program Status (Bit 4). . . . . . . . . . ... .. . ... . . .. .. ... .... .. .. .. . . . . ... .. . ... . . ... 29
VPP Status (Bit 3) . . . . . . . . . . . . . ... .. . . .... .. . . ... ... .. . . . . . . . . . ... .. . ... . . ... 29
Program Suspend Status (Bit 2) . . . . . . . . .... .. ... . . . . . . ... .. . . ... .... ... .... ... . 29
Block Protection Status (Bit 1) . . . .... . . . .... ... .. .. .... . . . ... .. . ... . . . . ... . . . . . 30
Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . .... . . . ... .. .. . . . . .. . . . ... ... . ..... . 30
Table 17. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12. Flash Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. Flash Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . .... ... 32
Table 19. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . .... .. ... . . . . . 33
Figure 14. Flash Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . .... .. . . . . . . . 34
Table 20. Flash Write AC Characteristics, Chip Enable Controlled . . . . .... .... .. .. . . . . . 35
Figure 15. Flash Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . .... .. .36
Table 21. Flash Power-Up and Reset AC Characteristics . . . . . . . ... . ... . . . . .. . ... .. . . 36
SRAM DEVICE . . . . . . . . . . . . . . ... .. ... .. .. .... ... . . . . . . ... . . . . . . . . . . . . . . . ... . . . . . . . 37
SRAM SUMMARY DESCRIPTION. . . . . . . . . . . . . .... .... .. . . ... .. . . . . . . . . . ... . ... ... 37
Figure 16. SRAM Logic Diagram . . . . . . . . . . . . .... ... . . . . . . . . . . . . . ... . . . . . .... ... 37
SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .... ... . . . . . . . . ... . . . . 38
Read . . . . . . . .... . . . .... . . . . .. .. .. . . . . . ... . ... ... . ... ... .. . ... .. .. . . . . ... . . 38
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Standby/Power-Down . . . . . . . .... ... ... .... .. . . ... ... .. . . . . . . . . . ... .. . ... . . . ..38
Data Retention . . . . .... .. .. .. . . ... ... . . . .... . . . ... .. .. . . . . . ... . ... ... . . . . . ..38
Output Disable . . . . . . . . . . . . . . . . . . .... . ... ... . ... .. . . . . . . . . . ... . ... .... . ... ..38
Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL .. .39
Figure 18. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 22. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 20. SRAM Write AC Waveforms, WS Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 22. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . 43
Figure 23. SRAM Write Cycle Waveform, UBS and LBS Controlled, GS Low . . . . . . . . . . . . . 43
Table 23. SRAM Write AC Characteristics . . . . . . . . .... .. .. .. ... . . . . . . ... .. .. ... ... 44
Figure 24. SRAM Low VDDS Data Retention AC Waveforms, E1S or UBS /LBS Controlled . . 45
Table 24. SRAM Low VDDS Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . .... . . . .... . . . .... . . . . . . 46
Table 25. Top Boot Block Addresses, M36W216TI. .... . . . ... .. . . . . . . . . . . . ... . . . . . . .... 46
Table 26. Bottom Boot Block Addresses, M36W216BI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46