
ADDRESS SPACE
3
3-3
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
3.2 Operation Modes
The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by
MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately
in Section 6.6, "Programming the Internal Flash Memory."
Table 3.2.1 Operation Mode Settings
MOD0
MOD1
MOD2 (Note 1)
Operation mode (Note 2)
VSS
Single-chip mode
VSS
VCCE
VSS
External extension mode
VCCE
VSS
Processor mode (FP = VSS)
VCCE
VSS
(Settings inhibited)
–
VCCE
(Settings inhibited)
Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively.
Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above table,
see Section 6.6, "Programming the Internal Flash Memory."
The internal ROM and external extension areas are located differently depending on how operation mode is set.
(All other areas in the address space are located the same way.) The following diagram shows how the internal
ROM and external extension areas are mapped into the address space in each operation mode. (For flash
rewrite mode, see Section 6.6, "Programming the Internal Flash Memory.")
3.2 Operation Modes