
DMAC
9-12
9
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
DMA3 Channel Control Register 0 (DM3CNT0)
<Address: H’0080 0440>
123456
b7
b0
SADSL3 DADSL3
MDSEL3 TREQF3
REQSL3
TENL3
TSZSL3
00000000
<Upon exiting reset: H’00>
b
Bit Name
Function
R
W
0
MDSEL3
0: Normal mode
R
W
DMA3 transfer mode select bit
1: Ring buffer mode
1
TREQF3
0: Transfer not requested
R(Note 1)
DMA3 transfer request flag bit
1: Transfer requested
2, 3
REQSL3
00: Software start
R
W
DMA3 transfer request source select bit
01: SIO0_TXD (transmit buffer empty)
10: SIO1_RXD (reception completed)
11: Extended DMA3 transfer request source select
(DMA3 Channel Control Register 1)
4
TENL3
0: Disable transfer
R
W
DMA3 transfer enable bit
1: Enable transfer
5
TSZSL3
0: 16 bits
R
W
DMA3 transfer size select bit
1: 8 bits
6
SADSL3
0: Fixed
R
W
DMA3 source address direction select bit
1: Increment
7
DADSL3
0: Fixed
R
W
DMA3 destination address direction select bit
1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
9.2 DMAC Related Registers