10.8 TOU (Output-Related 24-Bit Timer)
MULTIJUNCTION TIMERS
10
10-169
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
b0
12
3456
b7
PO1DISGBP PO1DISGB
000
0000
0
PWM Output 1 Disable Control Register GB (PO1DISGBCR)
<Address: H'0080 0782>
<Upon exiting reset: H’00>
b
Bit Name
Function
R
W
0–5
No function assigned. Fix to "0."
00
6
PO1DISGBP
–
0
W
PO1DISGB write control bit
7
PO1DISGB
0: Enable output
R
W
P10/TO29–P15/TO34 output disable select bit
1: Disable output
These registers control output from the respective corresponding pins by enabling or disabling it. These pins
can be used to control three-phase PWM output using the TOU timer.
Three-phase PWM output can be forcibly disabled (placed in the high-impedance state) by controlling this
register. This function can be used for all of output modes or port outputs of TOU. However, use for other
modes (external bus, SIO mode, DRI mode and TOP output modes (TO0-TO5) port inputs) is prohibited. For
details, see Section 10.8.20, “PWM Output Disable Function.” Also, if this register is accessed for read, it
serves as a status register indicating whether PWM output is disabled.
To set this register, follow the procedure described below. (In the case of register Gm)
1. Write data "1" to the POnDISGm write control bit (POnDISGmP).
2. After 1 above, write data "0" to the POnDISGm write control bit (POnDISGmP) and data "0" or "1" to the
output disable select bit (POnDISGm).
Note: If theare are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2,
the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the
writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting.
However the writing cycle from RTD and DRI are not effected.
