
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8-16
8
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
b0
12
3456
b7
P20MD
P21MD
P22MD
P23MD
P24MD
P25MD
P26MD
P27MD
000
0000
0
P2 Operation Mode Register (P2MOD)
<Address: H’0080 0742>
<Upon exiting reset: H’00>
b
Bit Name
Function
R
W
0
P20MD
0: P20/DD24 (Note 1)
R
W
Port P20 operation mode bit
1: A23
1
P21MD
0: P21/DD25 (Note 1)
R
W
Port P21 operation mode bit
1: A24
2
P22MD
0: P22/DD26 (Note 1)
R
W
Port P22 operation mode bit
1: A25
3
P23MD
0: P23/DD27 (Note 1)
R
W
Port P23 operation mode bit
1: A26
4
P24MD
0: P24/DD28 (Note 1)
R
W
Port P24 operation mode bit
1: A27
5
P25MD
0: P25/DD29 (Note 1)
R
W
Port P25 operation mode bit
1: A28
6
P26MD
0: P26/DD30 (Note 1)
R
W
Port P26 operation mode bit
1: A29
7
P27MD
0: P27/DD31 (Note 1)
R
W
Port P27 operation mode bit
1: A30
Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input.
Notes: During single-chip mode, settings of this register have no effect, and the port functions as port input/output or DD input pin.
During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins
(A23-A30).
8.3 Input/Output Port Related Registers