參數(shù)資料
型號: M30245FCGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數(shù): 54/244頁
文件大小: 3535K
代理商: M30245FCGP
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Serial Communication
147
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
Bit 0 is the I2C mode select bit 1. When set to “1”, ports operate respectively as the SDAi data transmit/
receive pin, SCLi clock I/O pin and port. A delay circuit is added to SDAi transmission output, therefore after
SCLi is at “L” level, SDAi output changes. Port (SCLi) is designed to read pin level regardless of the content
of the port direction register. SDAi transmission output is initially set to port in this mode. Furthermore,
interrupt factors for the bus collision detection interrupt and UARTi transmission interrupt change respec-
tively to the start/stop condition detection interrupts, acknowledge non-detection interrupt and acknowledge
detection interrupt.
The start condition detection interrupt is generated when the falling edge at the SDAi pin is detected while
the SCLi pin is in “H” state. The stop condition detection interrupt is generated when the falling edge at the
SDAi pin is detected while the SCLi pin is in the “H” state.
The acknowledge non-detect interrupt is generated when the “H” level at the SDAi pin is detected at the 9th
rise of the transmission clock. The acknowledge detect interrupt is generated when the “L” level at the SDAi
pin is detected at the 9th fall of the transmission clock. Also, DMA transfer can be started when the ac-
knowledge is detected if UARTi transmission is selected as the DMAi request factor.
Bit 1 is the arbitration detection flag control bit. Arbitration detects a conflict between data transmitted at
SCLi rise and data at the SDAi pin. This detect flag is allocated to bit 11 in UARTi transmit buffer register
(addresses 036F16, 02EF16, 033F16, 032F16, 02FF16). It is set to “1” when a conflict is detected. With the
arbitration lost detect flag control bit, it can be selected to update the flag in units of bits or bytes. When this
bit is set to ‘1”, update is set to units of byte. If a conflict is still detected, the arbitration lost detect flag
control bit will be set to “1” at the 9th rise of the clock. When updating in units of byte, always clear (“0”
interrupt) the arbitration lost detect flag control bit after the first byte has been acknowledge but before the
next byte starts transmitting.
Bit 2 is the bus busy flag. It is set to “1” when the start condition is detected, and reset to ‘0” when the stop
condition is detected.
Bit 3 is the SCLi L synchronization output enable bit. When this bit is set to “1”, the port data register is set
to “0” in sync with the “L” level at the SCLi pin.
Bit 4 is the bus collision detection sampling clock select bit. The bus collision detection interrupt is gener-
ated when RxDi and TxDi level do not conflict with each other. When this bit is “0”, a conflict is detected in
sync with the rise of the transfer clock. When this bit is “1”, detection is made when Timer Ai (Timer
A3:UART0, Timer A4:UART1, Timer A0:UART2, Timer A3:UART3 and Timer A4:UART4) underflows. The
operation is shown in Figure 1.107.
Bit 5 is the transmission enable bit automatic clear select bit. By setting this bit to “1”, the transmission bit is
automatically reset to “0” when the bus collision detection interrupt factor bit is “1” (when a conflict is
detected).
Bit 6 is the transmit start condition select bit. By setting this bit to “1”, TxDi transmission starts in sync with
the rise at the RxDi pin.
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相關代理商/技術參數(shù)
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