
Serial Communication
145
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
UARTi (i=0 to 3) operate the I2C interface (simple I2C bus) using the UARTi special mode register (address
03A716, 036716, 033716, 032716) and UARTi special mode register 2 (addresses 03A616, 036616, 033616,
and 032616). UARTi address special functions using UARTi special mode register 3 (address 03A516,
036516, 033516, and 032516).
I2C Bus interface mode
The I2C bus interface mode is provided with UARTi. When the I2C mode select bit (bit 0 in addresses
03A716, 036716, 033716, and 032716) is set to “1”, the I2C bus interface circuit is enabled.
To use the I2C bus, set the SCLi and the SDAi of the master and slave to output. Also for UART0, 1 and 3,
set the data output select bit (bit 5 in address 03AC16, 036C16, and 032C16) to N-channel open drain
output. Note: UART2 TxD and RxD (P70 and P71) are always N-channel open drain outputs and require
external pull-up resistors.
Table 1.49 shows the relationship of the I2C mode select bit to control. To use the chip in the clock synchro-
nized serial I/O mode or UART mode, always set this bit to “0”. Figure 1.106 shows a block diagram of I2C
mode.
Table 1.49. I2C features
Note 1: When using I2C mode, set 0 1 0 in bits 2, 1, 0 of the UARTi transmit/receive mode register. Disable the CTS/
RTS function. Select MSB first function.
Note 2: To switch from one factor to another:
1. Disable the interrupt of the corresponding number.
2. Switch to another factor.
3. Reset the interrupt request flag of the corresponding number.
4. Set the interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when I
2C mode (I2C mode select bit = "1") is valid and serial
I/O is invalid.
Function
Normal mode (IICM=0)
I2C mode (IICM=1) (Note 1)
1
Cause of interrupt number 3 and 9
(Note 2)
Bus collision detection
Start condition detection or stop
condition detection
2
Cause of interrupt number 13 and
15 (Note 2)
UARTi transmit
No acknowledgement detection
(NACK)
3
Cause of interrupt number 2 and
21 (Note 2)
UARTi receive
Acknowledgment detection (ACK)
4
UARTi transmit output delay
Not delayed
Delayed
5
P63, P67, P70, P74 at the same
time UARTi is in use
TxDi (output)
SDAi (input/output) (Note 3)
6
P62, P66, P71, P75 at the same
time UARTi is in use
RxDi (input)
SCLi (input/output)
7
P61, P65, P72, P76 at the same
time UARTi is in use
CLKi
P61, P65, P72, P76
8
DMA1 factor at the same time
UARTi receive
Acknowledgement detection (ACK)
9
Noise filter width
15 ns
50 ns
10
Reading P71, P75
Reading the terminal when 0 is
assigned to the direction register
Reading the terminal regardless of
the value of the direction register
11
Initial value of UARTi output
"H" level (when 0 is assigned to
CLKi polarity select bit)
The value set in latch P70, P74 when
the port is selected (Note 3)