參數(shù)資料
型號： M30240MC-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 70/125頁
文件大?。?/td> 753K
代理商： M30240MC-XXXFP
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
51
CONFIDENTIAL
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Universal Serial Bus
INTST3, INTST5, INTST7 or INTST9 is set to a “1” by the USB FCU if (in Endpoint xOUT CSR):
Successfully receives a packet of data
OUTXCSR1 (OVER_RUN) bit is set
OUTXCSR4 (FORCE_STALL) bit is set
Figure 35:
USB Interrupt Status Register 2
INTST12 is set to a “1” by the USB FCU if an overrun or underrun condition occurs in any of the end-
points.
INTST13 is set to a “1” by the USB FCU if a USB reset signaling from the host is received. All other
USB internal registers is reset to their default values.
INTST14 is set to a “1” by the USB FCU if a USB resume signaling is received from the host.
INTST15 is set to a “1” by the USB FCU if a USB suspend signaling is received from the host.
The USB Interrupt Enable Registers, shown in Figure 36 and Figure 37, are used to enable the cor-
responding interrupt status conditions, which can generate a USB function interrupt. If the bit to a cor-
responding interrupt condition is “0”, that condition does not generate a USB function interrupt. If the
bit is a “1”, that condition can generate a USB function interrupt. Upon reset, all USB interrupt status
conditions are enabled except bit 7 of USB Interrupt Enable Register 2 (that is, suspend and resume
interrupt is disabled).
Figure 36:
USB Interrupt Enable Register 1
INTST8
USB Endpoint 4 In Interrupt Status Flag (bit 0)
INTST9
USB Endpoint 4 Out Interrupt Status Flag (bit 1)
Bit 3:2
Reserved (Read/Write “0”)
INTST12
USB Overrun/Underrun Interrupt Status Flag (bit 4)
INTST13
USB Reset Interrupt Status Flag (bit 5)
INTST14
USB Resume Signaling Interrupt Status Flag (bit 6)
INTST15
USB Suspend Signaling Interrupt Status Flag (bit 7)
0: No interrupt request issued
1: Interrupt request issued
MSB
7
LSB
0
INTST15
INTST14
INTST13
INTST12
Reserved
INTST9
INTST8
Access: R/W
Reset:
0016
Address: 030316
Reserved
INTEN0
USB Endpoint 0 In Interrupt Enable Bit (bit 0)
Bit 1
Reserved (Read/Write “0”)
INTEN2
USB Endpoint 1 IN Interrupt Enable Bit (bit 2)
INTEN3
USB Endpoint 1 OUT Interrupt Enable Bit (bit 3)
INTEN4
USB Endpoint 2 IN Interrupt Enable Bit (bit 4)
INTEN5
USB Endpoint 2 OUT Interrupt Enable Bit (bit 5)
INTEN6
USB Endpoint 3 IN Interrupt Enable Bit (bit 6)
INTEN7
USB Endpoint 3 OUT Interrupt Enable Bit (bit 7)
0: Interrupt disabled
1: Interrupt enabled
MSB
7
LSB
0
INTEN7
INTEN6
INTEN5
INTEN4
INTEN3
Reserved
INTEN0
Access: R/W
Reset:
FF16
INTEN2
Address: 030416
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