
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
45
CONFIDENTIAL
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Universal Serial Bus
Generic Function Interface
The GFI handles the all USB standard requests from the host through the control endpoint (endpoint zero),
handles Bulk, Isochronous and Interrupt transfers through endpoints 1-4. The GFI handles read pointer rever-
sal for re-transmit the current data set; write pointer reversal for reception of the last data set; data toggle syn-
chronization.
Serial Engine Interface Unit
The SIU block decodes the Address and Endpoint fields from the USB host.
Microcontroller Interface
The MCI block handles the Microcontroller interface and performs address decoding and synchronization of
control signals.
USB Transceiver
The USB transceiver, designed to interface with the physical layer of the USB, is compliant with the USB
Specification (version 1.0) for high speed devices. It consists of two 6-ohm drivers, a receiver, and schmitt
triggers for single-ended receive signals.
The transceiver also includes a voltage converter. The voltage converter can supply 3.0 - 3.6V to the trans-
mitter when the rest of the chip (CPU, USB FCU) operates at 4.15 - 5.25V. To enable the voltage converter,
set bit 4 of the USB Control Register (USBC) to a “1”. To disable the voltage converter, set bit 4 of the USBC
to a “0”. Refer to Section 5.5 “USB Transceiver” for more detailed information.
Figure 29:
USB Function Control Unit Block Diagram
USB Interrupts
There are two types of USB interrupts in this device: the first type is the USB function (including overrun/un-
derrun USB, reset, suspend and resume) interrupt, used to control the flow of data and USB power control;
the second type is start-of-frame (SOF) interrupt, used to monitor the transfer of isochronous (ISO) data.
USB Function Interrupt
Endpoints 1-4 each have two interrupt status bits associated with them to control the data transfer or to report
a STALL/UNDER_RUN/OVER_RUN condition. The EPx_OUT_INT bit is set when the USB FCU successfully
receives a packet of data, or sets the FORCE_STALL bit, or the OVER_RUN bit of the Endpoint x OUT CSR.
The EPx_IN_INT bit is set when the USB FCU successfully sends a packet of data, or sets the UNDER_RUN
bit of the Endpoint x IN CSR. Endpoint 0 - the control endpoint - has one interrupt status bit associated with it
to control the data transfer or report a STALL condition. The EP0_INT is set when the USB FCU successfully
receives/sends a packet of data, or sets the SETUP_END bit, the FORCE_STALL bit, or clears the
DATA_END bit in the Endpoint 0 IN CSR. Each endpoint interrupt is enabled by setting the corresponding bit
in the USB Interrupt Enable Register 1 and 2. The USB Interrupt Status Register 1 and 2 are used to indicate
CPU
MCI
SIU
GFI
FIFOs
SIE
T
ransceiv
er
D+
D-