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參數(shù)資料
| 型號(hào)： | M16550 |
| 廠商： | Lineage Power |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收器/傳送器） |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 124K |
| 代理商： | M16550 |
August 99
M16550 UART MACRO
Data Sheet
Logic Design Solutions
9/11
1.5.8
MODEM status register
The MODEM status register enables the microprocessor to examine the condition of the modem interface inputs.
BIT
0
SIGNAL
FCTS
DESCRIPTION
Front clear to send. Active high. Indicates that the CTS input has changed since the processor read the
modem status register.
Generates a modem status interrupt.
This bit is cleared once it has been read.
Front data set ready. Active high. Indicates that the DSR input has changed since the processor read
the modem status register.
Generates a modem status interrupt.
This bit is cleared once it has been read.
Front ring indicator. Active high. Indicates that the RI input has changed from 0 to 1 since the
processor read the modem status register.
Generates a modem status interrupt.
This bit is cleared once it has been read.
Front data carrier. Active high. Indicates that the DCD input has changed since the processor read the
modem status register.
Generates a modem status interrupt.
This bit is cleared once it has been read.
Clear To Send. This bit is the state of the pin CTS.
Data Set Ready. This bit is the state of the pin DSR.
Ring Indicator. This bit is the state of the pin RI.
Data Carrier Detect. This bit is the state of the pin DCD.
1
FDSR
2
FRI
3
FDCD
4
5
6
7
CTS
DSR
RI
DCD
1.5.9
Receiver buffer register
The receiver buffer register is a read only register that contains the last complete data word sample received by the
UART. The microprocessor is advised by an interrupt signal.
1.5.10
Transmitter buffer register
The transmitter buffer register is a write only register that loads the next data byte to be transmitted by the UART. The
microprocessor is advised by an interrupt signal that this register is empty.
1.5.11
Transmitter FIFO
The transmitter FIFO is only active in FIFO mode. In FIFO mode, as soon as there is a data in the FIFO, this one is sent to
the transmission logic. The FIFO is protected against overwritting from the user, it means when the FIFO is full, the next
data coming from the user will not be written in the FIFO.
When the read pointer reaches his transmission trigger level the microprocessor is advised by an interrupt.
1.5.12
Receiver FIFO
The receiver FIFO is only active in FIFO mode. In FIFO mode, as soon as the writting pointer reaches his reception trigger
level the microprocessor is advised by an interrupt signal. The FIFO is protected against overwritting from the reception
side, it means when the FIFO is full the next data received is not written in the FIFO.
The reception FIFO is also protected against overreading from the user side, it means if the FIFO is empty the read pointer
is not incremented.
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