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參數(shù)資料
| 型號： | M16550 |
| 廠商： | Lineage Power |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收器/傳送器） |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 124K |
| 代理商： | M16550 |
August 99
M16550 UART MACRO
Data Sheet
Logic Design Solutions
8/11
1.5.6
Interrupt Enable Register
The interrupt enable register selectively enables or disable four different sources of interruption. When a bit is at 0, the
interrupt is not enabled.
Bit
0
Signal
RDA
Description
Received data available. Enables interrupts when receive data is loaded in the receiver buffer register or
when the Receiver FIFO has reached its trigger level.
Transmitter buffer register empty. Enables interrupts when the Transmitter buffer register is empty or
when the Transmitter FIFO has reached its trigger level.
Receiver line status. Enables interrupts when the Receiver line status register changes state.
Modem status. Enables interrupts when the Modem status register changes state.
Not used.
1
THRE
2
3
RLS
MS
-
7 :4
1.5.7
MODEM Control Register
The MODEM Control Register controls the modem interface outputs.
BIT
0
1
2
3
4
SIGNAL
DTR
RTS
OUT1
OUT2
LOOP
DESCRIPTION
Data Terminal Ready. The user can program the DTR bit to control the DTR output.
Request To Send. The user can program the RTS bit to control the RTS output.
Output 1. The user can program the OUT1 bit to control the OUT1 output.
Output 2. The user can program the OUT2 bit to control the OUT2 output.
Enable loopback. Active high. Connection are as follows :
-
The SOUT output is set to high.
-
The SIN input is ignored.
-
The internal SOUT is connected to the internal SIN.
-
The MODEM control inputs are ignored.
-
The MODEM control outputs are used internally in place of the modem control inputs.
The connections are as follows :
DTR
=> DSR
RTS
=> CTS
OUT1
=> RI
OUT2
=> DCD
2..7
Not used.
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