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參數(shù)資料
| 型號(hào)： | M16550 |
| 廠商： | Lineage Power |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收器/傳送器） |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大小： | 124K |
| 代理商： | M16550 |
August 99
M16550 UART MACRO
Data Sheet
Logic Design Solutions
7/11
1.5.4
FIFO Control Register
The FIFO Control Register sets the FIFO mode used by the UART macro.
BIT
0
DESCRIPTION
Sets the FIFO mode. At one the FIFO counter logic is reset.
The following bits are taken into account if bit 0 is set to one.
Active high. Reset the Receiver FIFO counter logic. The Receiver shift register is not cleared.
Once take into account this bit is automatically cleared.
Active high. Reset the Transmitter FIFO counter logic. The Transmitter shift register is not cleared.
Once take into account this bit is automatically cleared.
Not used.
Sets the trigger level for the Transmitter FIFO:
00 : 1 byte | 01 : 4 bytes | 10 : 8 bytes | 11 : 12 bytes |
When the trigger level has been reached, it remains 1, 4, 8 or 12 bytes to transmit in the Transmitter FIFO.
Sets the trigger level for the Receiver FIFO:
00 : 1 byte | 01 : 4 bytes | 10 : 8 bytes | 11 : 12 bytes |
When the trigger level has been reached, there is 1, 4, 8 or 12 bytes in the Receiver FIFO.
1
2
3
4..5
6..7
1.5.5
Interrupt Identification Register
This register enables the microprocessor to identify the interrupt coming from the macro UART.
BIT
0
1
2
3
Interrupt Type
Receiver Status
Receiver buffer register
full
Receiver data available
Or
Receiver FIFO has
Reached its trigger
level
Transmitter buffer
register empty
Transmitter buffer
register empty
Or
Transmitter FIFO has
Reached its trigger
level
Read the interrupt ID
register
Or
Write to Transmitter
buffer register
Or
Write to Transmitter
FIFO to drop below the
trigger level.
MODEM Status
Interrupt Source
Overrun, Parity, Frame
error, break interrupt.
CTS, DSR, RI or
DCD change state.
Interrupt Reset
Read the Line status
register.
Read the Receiver
buffer register
Or
Read the Receiver
FIFO to drop below the
trigger level.
Read the MODEM
status register.
BIT
4
5
6
7
DESCRIPTION
Not used.
Not used.
At one when in
FIFO mode.
(FIFO Control Register
Bit 0 at one)
At one when in
FIFO mode.
(FIFO Control
Register Bit 0 at one)
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