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參數(shù)資料
| 型號(hào)： | M16550 |
| 廠商： | Lineage Power |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收器/傳送器） |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 124K |
| 代理商： | M16550 |
August 99
M16550 UART MACRO
Data Sheet
Logic Design Solutions
5/11
1.4 Register Address Map
The state of the A[2:0], WR and RD signals determines which internal register the microprocessor addresses.
DIV
0
0
1
0
1
x
x
x
x
x
x
x
WR
0
1
1
1
1
0
1
1
1
0
0
x
RD
1
0
0
0
0
1
0
0
0
1
1
x
A(2:0)
000
000
000
001
001
010
010
011
100
101
110
111
REGISTER
Receiver buffer register. (read only)
Transmitter buffer register. (write only)
Divisor register (LSB).
Interrupt enable register.
Divisor register (MSB).
Interrupt ID register.
FIFO control register.
Line control register.
MODEM control register.
Line status register.
MODEM status register.
Not used.
The DIV bit allows access to the divisor register. The DIV is bit 6 of the line control register.
1.5 Registers
1.5.1
Line Control Register
The line Control Register sets the data and communication formats used by the UART macro.
BIT
1..0
DESCRIPTION
Sets the length of the word associated with the transmitted or received word :
00 : 5 bits | 01 : 6 bits | 10 : 7 bits | 11 : 8 bits |
Controls the number of STOP bits generated by the transmitter section :
0 : 1 bit STOP
1 : 2 bit STOP
The receiver always checks only for the first bit STOP.
Active high. Enable parity generation in the transmitter section and parity checking in the receiver section.
The parity bit is inserted between the last word bit and the first STOP bit.
Parity Control. Generates/checks an odd/even number of logic one bits in data word + parity bit.
1 : Even parity.
0 : Odd parity.
Break Control. Active high. The macro UART generates a break condition, which is SOUT at low level for at least
one full word transmission. The SOUT output is at 1 by default.
DIV. Active high. Enable access to the divisor register.
Not used.
2
3
4
5
6
7
1.5.2
Divisor register
The baud rate generator is composed of a programmable clock divider. The clock divider is made up of a 16-bit counter,
loaded by the value of the divisor register.
The result of the division is the system clock divided by the register divisor value.
For example if the system clock is 50MHz, this latter is divided by the register divisor value, for example 325\d, we get
50MHz /(325) = 153,846 KHz, this is the BAUDOUT signal. Then to get the baud rate, this value has to be divided by 16,
so 153,846 KHz / 16 = 9615,38 bits/s (9600 bits/s).
The Baudout signal is a positive pulse of one system clock period. The baudout signal is used by the recipient in order to
sample 16 times the received bits. The recipient uses the baudout clock to create a middle clock, which is placed in the
middle time of the received bits.
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