參數(shù)資料
型號(hào): M16550
廠商: Lineage Power
英文描述: Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器)
中文描述: 通用異步接收器/發(fā)送器(通用異步接收器/傳送器)
文件頁數(shù): 6/11頁
文件大?。?/td> 124K
代理商: M16550
August 99
M16550 UART MACRO
Data Sheet
Logic Design Solutions
6/11
1.5.3
Line Status Register
The Line Status Register enables the host processor to examine data transfers.
BIT
0
SIGNAL
RDR
DESCRIPTION
Receiver Data Ready. Active high.
Indicates that an incoming word has been received and transferred to the receiver buffer register.
In FIFO mode, the Receiver FIFO has reached its trigger level.
Generates a receive data available interrupt.
This bit is cleared once it has been read.
Overrun error. Active high.
Indicates that new data has been written over unread data in the receiver buffer register.
In FIFO mode, when the FIFO is full, indicates a new data has been received in the receiver shift
register. The character in the the receiver shift register is overwritten and not written in the receiver
FIFO.
Generates a line status interrupt.
This bit is cleared once it has been read.
Parity error. Active high.
Indicates that newly received data has incorrect parity.
In FIFO mode, this error is registered with each character received. This error is revealed with the
character at the top of the Receiver FIFO.
Generates a line status interrupt. In FIFO mode, one line status interrupt is generated for each
received character containing a parity error.
This bit is cleared once it has been read.
Framing error. Active high.
Indicates that newly received data had incorrect stop bit.
In FIFO mode, this error is registered with each character received. This error is revealed with the
character at the top of the Receiver FIFO.
Generates a line status interrupt. In FIFO mode, one line status interrupt is generated for each
received character containing a framing error.
This bit is cleared once it has been read.
Break interrupt. Active high.
Indicates that a break condition was detected on the serial input. A break condition occurs when the
serial data in is held at logic low for longer than full word transmission.
In FIFO mode, this error is registered with only the first break character received.
When break occcurs, only one zero character is loaded into the Receiver FIFO. The next character is
written in the Receiver FIFO on the next valid start detected.
Generates a line status interrupt.
This bit is cleared once it has been read.
Transmitter buffer register empty. Active high.
Indicates that the UART macro is ready to accept a new data word from the microprocessor for
transmission.
In the FIFO mode this bit is set to one when the Transmitter FIFO has reached its trigger level.
Generates Transmitter buffer register empty interrupt.
This bit is cleared once it has been read or by reading the interrupt ID register or by writing to the
Transmitter buffer register or by writing to Transmitter FIFO to drop below the trigger level.
Transmitter empty. Active high.
Indicates that the Transmitter buffer register and the serial transmitter register are both empty.
In the FIFO mode, indicates the Transmitter FIFO and the serial transmitter register are both empty.
This bit is cleared once it has been read.
FIFO contains error. Active high.
In the 16450 mode this bit is at 0.
In the FIFO mode this bit is set to one when there is at least one parity error, framing error or break
indication in the FIFO.
This bit is cleared once it has been read.
1
OE
2
PE
3
FE
4
BI
5
TBRE
6
TRE
7
F_ERR
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