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參數(shù)資料
| 型號： | M16450 |
| 廠商： | Lineage Power |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收器/傳送器） |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 112K |
| 代理商： | M16450 |
January 99
M16450 UART MACRO
Data Sheet
Logic Design Solutions
9/10
1.6 Write cycle
The write cycle is made up of a positive pulse of the WR signal sampling by the system clock.
The WR signal enables the decoding of the 3 address signals A(2 :0). The data should be present at the same time.
The following chronogram describes the write cycle :
CK
WR
AD
DATA
The Setup and hold timings are implementation-dependent.
If the macro is used alone in the FPGA, the timing will be equal to that of the I/O of the FPGA. Please refer to the
appropriate FPGA data sheet.
If the macro is used in a design, these timings will be controlled by the Place and Route software because of the
synchronous conception.
1.7 Read cycle
The read cycle is initialized as soon as and while the RD signal is at level 1. This signal should be synchronous to the
system clock.
The following chronogram describes the write cycle :
CK
RD
AD
DATA
ZZ
DATA
ZZ
The Setup and hold timings are implementation-dependent.
If the macro is used alone in the FPGA, the timing will be equal to that of the I/O of the FPGA. Please refer to the
appropriate FPGA data sheet.
If the macro is used in a design, because of the synchronous conception, these timings will be controlled by the Place and
Route software.
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