- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384634 > M16450 (Lineage Power) Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) PDF資料下載
參數(shù)資料
| 型號(hào)： | M16450 |
| 廠商： | Lineage Power |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收器/傳送器） |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大小： | 112K |
| 代理商： | M16450 |
January 99
M16450 UART MACRO
Data Sheet
Logic Design Solutions
5/10
1.4 Register Address Map
The state of the A[2:0], WR and RD signals determines which internal register the microprocessor addresses.
DIV
0
0
1
0
1
x
x
x
x
x
x
WR
0
1
1
1
1
0
1
1
0
0
x
RD
1
0
0
0
0
1
0
0
1
1
x
A(2:0)
000
000
000
001
001
010
011
100
101
110
111
REGISTER
Receiver buffer register. (read only)
Transmitter buffer register. (write only)
Divisor register (LSB).
Interrupt enable register.
Divisor register (MSB).
Interrupt ID register.
Line control register.
MODEM control register.
Line status register.
MODEM status register.
Not used.
The DIV bit allows access to the divisor register. The DIV is bit 6 of the line control register.
1.5 Registers
1.5.1
Receiver buffer register
The receiver buffer register is a read only register that contains the last complete data word sample received by the
UART. The microprocessor is advised by an interrupt signal.
1.5.2
Transmitter buffer register
The transmitter buffer register is a write only register that loads the next data byte to be transmitted by the UART. The
microprocessor is advised by an interrupt signal that this register is empty.
1.5.3
Divisor register
The baud rate generator is composed of a programmable clock divider. The clock divider is made up of a 16-bit counter,
loaded by the value of the divisor register.
The result of the division is the system clock divided by the register divisor value.
For example if the system clock is 50MHz, this latter is divided by the register divisor value, for example 325\d, we get
50MHz /(325) = 153,846 KHz, this is the BAUDOUT signal. Then to get the baud rate, this value has to be divided by 16,
so 153,846 KHz / 16 = 9615,38 bits/s (9600 bits/s).
The Baudout signal is a positive pulse of one system clock period. The baudout signal is used by the recipient in order to
sample 16 times the received bits. The recipient uses the baudout clock to create a middle clock, which is placed in the
middle time of the received bits.
1.5.4
Interrupt Enable Register
The interrupt enable register selectively enables or disable four different sources of interruption. When a bit is at 0, the
interrupt is not enabled.
Bit
0
1
2
3
7 :4
Signal
RDA
THRE
RLS
MS
-
Description
Received data available. Enables interrupts when receive data is loaded in the receiver buffer register.
Transmitter buffer register empty. Enables interrupts when the Transmitter buffer register is empty.
Receiver line status. Enables interrupts when the Receiver line status register changes state.
Modem status. Enables interrupts when the Modem status register changes state.
Not used.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M16550 | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| M2035S | High-Voltage Trench MOS Barrier Schottky Rectifier |
| M2045S | High-Voltage Trench MOS Barrier Schottky Rectifier |
| M2125 | SINGLE-SUPPLY OPERTIONAL AMPLIFIER |
| M2125-AF5-0-R | SINGLE-SUPPLY OPERTIONAL AMPLIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1645-10M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| M1645-410M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| M1646 SL001 | 制造商:Alpha Wire Company 功能描述:CBL 6COND 22AWG SLT 1000' |
| M1646 SL002 | 制造商:Alpha Wire Company 功能描述:CBL 6COND 22AWG SLT 500' |
| M1646 SL005 | 制造商:Alpha Wire Company 功能描述:CBL 6COND 22AWG SLT 100' |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。