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參數(shù)資料
| 型號(hào)： | M16450 |
| 廠商： | Lineage Power |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收器/傳送器） |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 112K |
| 代理商： | M16450 |
January 99
M16450 UART MACRO
Data Sheet
Logic Design Solutions
6/10
1.5.5
Interrupt Identification Register
This register enables the microprocessor to identify the interrupt coming from the macro UART.
BIT
0
1
2
3
Interrupt Type
Receiver Status
Receiver buffer register
full
Receiver data available
Transmitter buffer
register empty
Transmitter buffer
register empty
Read the interrupt ID
register
Or
Write to Transmitter
buffer register.
MODEM Status
Interrupt Source
Overrun, Parity, Frame
error, break interrupt.
Read the Line status
register.
CTS, DSR, RI or
DCD change state.
Read the MODEM
status register.
Interrupt Reset
Read the Receiver
buffer register.
Bits 4 to 7 are read at 0.
1.5.6
Line Control Register
The line Control Register sets the data and communication formats used by the UART macro.
BIT
1..0
DESCRIPTION
Sets the length of the word associated with the transmitted or received word :
00 : 5 bits | 01 : 6 bits | 10 : 7 bits | 11 : 8 bits |
Controls the number of STOP bits generated by the transmitter section :
0 : 1 bit STOP
1 : 2 bit STOP
The receiver always checks only for the first bit STOP.
Active high. Enable parity generation in the transmitter section and parity checking in the receiver section.
The parity bit is inserted between the last word bit and the first STOP bit.
Parity Control.
1 : Even parity.
0 : Odd parity.
Break Control. Active high. The macro UART generates a break condition, which is SOUT at low level for at least
one full word transmission. The SOUT output is at 1 by default.
DIV. Active high. Enable access to the divisor register.
Not used.
2
3
4
5
6
7
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