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參數(shù)資料
| 型號(hào)： | M16450 |
| 廠商： | Lineage Power |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收器/傳送器） |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 112K |
| 代理商： | M16450 |
January 99
M16450 UART MACRO
Data Sheet
Logic Design Solutions
3/10
1. Description
1.1 Symbol
M16450 UART MACRO
1.2 Pin Description
Signal
CLOCK
ASYNC_
RESET
A(2 :0)
D(7 :0)
RD
WR
Type
Input
Input
Activity
-
low
Description
System clock. Rising edge triggered. Provides the master timing reference.
System asynchronous reset of the FPGA.
Input
I/O
Input
Input
-
-
Address signals to decode the internal registers.
Data bus.
A read cycle is active until RD is active.
The current data on the data bus is written in the internal register with a clock
pulse of WR. See Cycle diagram.
Interrupt. Indicates that an enabled interrupt condition has been met.
high
high
INT
Output
high
SOUT
SIN
RTS
Output
Input
Output
low
low
low
Output of the Transmitter.
Serial data input of the Receiver.
Request To Send. The UART macro is ready to exchange data. This output is
controlled by writing to bit 1 of the modem control register.
Clear To Send. Indicates that the modem is ready to exchange data. A change
in input is recorded in bit 0 of the modem status register. If the modem status
interrupt is enabled, an interrupt is generated.
Data Terminal Ready. The UART macro is ready to exchange data. This
output is controlled by writing to bit 0 of the modem control register.
Data Set Ready. Indicates that the modem is ready to establish the
communications link with the UART macro. A change in input is recorded in
bit 1 of the modem status register. If the modem status interrupt is enabled, an
interrupt is generated.
Data Carrier Detect. Indicates that the modem detected a data carrier. A
change in input is recorded in bit 3 of the modem status register. If the
modem status interrupt is enabled, an interrupt is generated.
Ring Indicator. Indicates that the modem detected the ring signal. A change in
input is recorded in bit 2 of the modem status register. If the modem status
interrupt is enabled, an interrupt is generated.
General purpose output 1. This output is controlled by writing to bit 2 of the
modem control register.
General purpose output 2. This output is controlled by writing to bit 3 of the
modem control register.
CTS
Input
low
DTR
Output
low
DSR
Input
low
DCD
Input
low
RI
Output
low
OUT1
Output
-
OUT2
Output
-
WR
RD
D[7..0]
INT
A[2:0]
SOUT
SIN
RTS
CTS
DTR
DSR
DCD
RI
CK
RESET
OUT1
OUT2
BAUDOUT
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