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參數資料
| 型號： | M16450 |
| 廠商： | Lineage Power |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收器/傳送器） |
| 文件頁數： | 7/10頁 |
| 文件大?。?/td> | 112K |
| 代理商： | M16450 |
January 99
M16450 UART MACRO
Data Sheet
Logic Design Solutions
7/10
1.5.7
MODEM Control Register
The MODEM Control Register controls the modem interface outputs.
BIT
0
1
2
3
4
SIGNAL
DTR
RTS
OUT1
OUT2
LOOP
DESCRIPTION
Data Terminal Ready. The user can program the DTR bit to control the DTR output.
Request To Send. The user can program the RTS bit to control the RTS output.
Output 1. The user can program the OUT1 bit to control the OUT1 output.
Output 2. The user can program the OUT2 bit to control the OUT2 output.
Enable loopback. Active high. Connection are as follows :
-
The SOUT output is set to high.
-
The SIN input is ignored.
-
The internal SOUT is connected to the internal SIN.
-
The MODEM control inputs are ignored.
-
The MODEM control outputs are used internally in place of the modem control inputs.
The connections are as follows :
DTR
=> DSR
RTS
=> CTS
OUT1
=> RI
OUT2
=> DCD
2..7
Not used.
1.5.8
Line Status Register
The Line Status Register enables the host processor to examine data transfers.
BIT
0
SIGNAL
RDR
DESCRIPTION
Receiver Data Ready. Active high. Indicates that an incoming word has been received and
transferred to the receiver buffer register.
Generates a receive data available interrupt.
This bit is cleared once it has been read.
Overrun error. Active high. Indicates that new data has been written over unread data in the receiver
buffer register.
Generates a line status interrupt.
This bit is cleared by reading this register.
Parity error. Active high. Indicates that newly received data has incorrect parity.
Generates a line status interrupt.
This bit is cleared once it has been read.
Framing error. Active high. Indicates that newly received data had incorrect stop bit.
Generates a line status interrupt.
This bit is cleared once it has been read.
Break interrupt. Active high. Indicates that a break condition was detected on the serial input. A
break condition occurs when the serial data in is held at logic low for longer than full word
transmission.
Generates a line status interrupt.
This bit is cleared once it has been read.
Transmitter buffer register empty. Indicates that the UART macro is ready to accept a new data
word from the microprocessor for transmission.
Generates Transmitter buffer register empty interrupt.
This bit is cleared by Read the interrupt ID register or by writing to the Transmitter buffer register.
Transmitter empty. Indicates that the Transmitter buffer register and the serial transmitter register
are both empty.
This bit is cleared once it has been read.
Not used. Read at 0.
1
OE
2
PE
3
FE
4
BI
5
TBRE
6
TRE
7
-
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