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參數(shù)資料
| 型號： | M13S128324A-6BG |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Modify typing error of Pin Arrangement |
| 中文描述： | 修改輸入錯誤的管腳配置 |
| 文件頁數(shù)： | 27/48頁 |
| 文件大小： | 803K |
| 代理商： | M13S128324A-6BG |
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ES MT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 27/48
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with
WE
high at the rising edge of the
clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the
self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce
power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP
command and then asserting CKE high for longer than t
XSRD
for locking of DLL.
C L K
C L K
Power down
Power down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is
referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CLK, CLK and CKE.
For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that case, the DLL must
be enabled after exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However,
power-down duration is limited by the refresh requirements of the device, so in most applications, the self-refresh mode is preferred
over the DLL disable power-down mode. In the power-down, CKE LOW and a stable clock signal must be maintained at the inputs
of the DDR SDRAM, and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is
registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later.
CO MM AN D
CKE
t
X S N R
RSelf
RAuto
Read
t
X S R D
CO M M AN D
CKE
C L K
C L K
VALID
NOP
NOP
VALID
Enter power-down
mode
No column
acess
in program
t
IS
t
IS
Exit power-down
mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M13S128324A-6BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A-6LG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A-6LIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S2561616A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S2561616A_09 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Double Data Rate SDRAM |
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