參數(shù)資料
型號: M13S128324A-6BG
廠商: Electronic Theatre Controls, Inc.
英文描述: Modify typing error of Pin Arrangement
中文描述: 修改輸入錯誤的管腳配置
文件頁數(shù): 12/48頁
文件大小: 803K
代理商: M13S128324A-6BG
ES MT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 12/48
Burst Address Ordering for Burst Length
Starting
Address (A2, A1,A0)
xx0
xx1
x00
x01
x10
x11
000
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
010
2, 3, 4, 5, 6, 7, 0, 1
011
3, 4, 5, 6, 7, 0, 1, 2
100
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
110
6, 7, 0, 1, 2, 3, 4, 5
111
7, 0, 1, 2, 3, 4, 5, 6
Burst
Length
Sequential Mode
Interleave Mode
0, 1
1, 0
0, 1
1, 0
2
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
4
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is
enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S32321A also support a weak drive strength
option, intended for lighter load and/or point-to-point environments.
Mode Register Set
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum t
RP
is required to issue MRS command.
0
1
2
3
4
5
6
7
8
CO MM AN D
t
C K
Al l B a n k s
R e g Mo d e
CoAn y
t
R P
* 2
* 1
CLK
CLK
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