參數(shù)資料
型號(hào): M13S128324A-6BG
廠商: Electronic Theatre Controls, Inc.
英文描述: Modify typing error of Pin Arrangement
中文描述: 修改輸入錯(cuò)誤的管腳配置
文件頁(yè)數(shù): 21/48頁(yè)
文件大?。?/td> 803K
代理商: M13S128324A-6BG
ES MT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 21/48
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one
clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered,
any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (t
WTR
) is
required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated
will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write
command.
<Burst Length = 8, CAS Latency = 3>
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into
the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where
the Write to Read delay is 1 clock cycle is disallowed.
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately
precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory
controller) in time to allow the buses to turn around before the SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS inputs is ignored by the SDRAM.
5. It is illegal for a Read command interrupt a Write with autoprecharge command.
C A S L at e n c y= 3
0
1
2
3
4
5
6
7
8
CO M M AN D
DQS
DQ 's
C A S L at e n c y= 3
DQS
DQ 's
NOP
NOP
NOP
NOP
Read
NOP
NOP
NOP
t
D Q S S m a x
D i n 0 Di n 1
W RITE
t
W P R E S
t
W T R
D i n 2
D i n 3
Di n 4 Di n 5 D i n 6 D in 7
Dout 0 Dout 1
t
D Q S S m i n
D i n 0 D in 1
t
W P R E S
t
W T R
Di n 2
D i n 3 D i n 4 Di n 5 D i n 6 D i n 7
Dout 0 Dout 1
D M
C L K
C L K
相關(guān)PDF資料
PDF描述
M1512 8 FUNCTIONS 5 LED FLASH IC
M1632 Liquid Crystal Display Modules
M1641 Liquid Crystal Display Modules
M170EG01VA 17.0” SXGA Color TFT-LCD
M18109A Built-in oscillator.
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M13S128324A-6BIG 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-6LG 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-6LIG 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A_09 制造商:ESMT 制造商全稱(chēng):Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Double Data Rate SDRAM