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參數(shù)資料
| 型號(hào)： | LXP730LE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 5/70頁 |
| 文件大?。?/td> | 1007K |
| 代理商： | LXP730LE |
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Datasheet
5
Multi-Rate DSL Framer
—
LXP730
5.13.24 DX Z Bits 33 - 40....................................................................................68
5.13.25 DX Z Bits 41 - 48....................................................................................68
Reserved Registers (2 bytes)..............................................................................68
Interrupt Registers (2 bytes)................................................................................69
5.15.1 Interrupt Enables....................................................................................69
5.15.2 Interrupt Status.......................................................................................69
Mechanical Specifications
....................................................................................70
5.14
5.15
6.0
Figures
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26
LXP730 Block Diagram.........................................................................................9
LXP730 Pin Assignments....................................................................................10
Clock Generation and Distribution.......................................................................22
Frame Format for N=12.......................................................................................26
Activation State Machine.....................................................................................27
High Performance Voice/Data Transport ............................................................28
Pair Gain Transport.............................................................................................29
T1/E1 Fractional Transport..................................................................................29
IOM Adaption Circuitry........................................................................................30
Multiple Interrupt Line Circuit...............................................................................32
Generic PCM Interface Timing............................................................................34
PCM Timing, 1X Clock........................................................................................35
PCM Timing, 2X Clock........................................................................................36
Codec Interface Timing.......................................................................................37
Asynchronous Port Timing..................................................................................38
OSIO Timing........................................................................................................39
MDSL Interface Input Timing...............................................................................40
MDSL Interface Output Timing............................................................................40
E1/T1 Input Timing..............................................................................................41
E1/T1 Output Timing...........................................................................................41
Microprocessor Write Cycle - Motorola Mode .....................................................42
Microprocessor Read Cycle - Motorola Mode.....................................................43
Microprocessor Write Cycle - Intel Mode ............................................................44
Microprocessor Read Cycle - Intel Mode............................................................45
Reset Timing.......................................................................................................45
64 - Pin LQFP Package Specification.................................................................70
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