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參數(shù)資料
| 型號： | LXP730LE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 16/70頁 |
| 文件大?。?/td> | 1007K |
| 代理商： | LXP730LE |
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LXP730
—
Multi-Rate DSL Framer
16
Datasheet
The slip buffer is two frame lengths long. The buffer will empty if the PCM clock is reading data
out of the slip buffer faster than the TSI is writing into it. When the last bit for the frame has been
read and there is not another byte from the next frame to clock out, the read pointer is set back to
the beginning of the current frame and repeated. The other slip situation occurs when the TSI is
writing data faster than the PCM is clocking it out. When the write pointer gets close to the read
pointer that hasn
’
t finished a frame, then the read pointer is allowed to finish the current frame and
then is advanced to skip the next frame.
The slip buffer may be bypassed by setting the SBBP bit, (bit 0, in the PCM_CFG1, register). Slip
occurrences are detected and signalled in the Interrupt Status register.
Normally the LXP730 PCM bus is configured as a slave in the Local unit, while the Remote
LXP730 PCM bus can be either configured as slave or master off the PCM bus. When the Remote
LXP730 is in PCM slave mode, the slip buffers accommodate the differences in the two PCM
clocks. When the Remote LXP730 is in PCM master mode, the PCM clock and frame pulse are
derived from the receive DSL clock using the internal ADPLL to provide loop timing to prevent
the slip action from occurring.
The PCM bus timeslot assignments to the DSL channels may be altered while the DSL link is
active. The Nx registers can be changed without interfering with other Nx registers and the effect
of their settings.
The PDO pin is tri-stated except during programmed time slots.
The PFRM pulse defines the start of a PCM frame. The number of PCM time slots per frame is
variable from 4 to 64. This is programmed by setting the six MAXPCHN bits in, the PCM_CFG2
register, with the value n-1 number time slots.
PCM selection for a MDSL channel is accomplished by setting the CH_CFG bits in the Nx register
to
‘
10
’
(binary).
2.4
Codec Interface
The LXP730 primarily supports the COMBO codec I style devices. The LXP730 codec interface is
programmable to allow the use of other codec type devices that require a positive frame pulse. The
LXP730 provides a separate set of pins for this interface allowing simultaneous operation with a
PCM bus with the following characteristics:
Short frame positive sync pulse
Clock at 1x or 2x the data rate
Programmable number of bytes per frame in MPC; 8, 16, 32, 64
The data rates can range from 256 kbps to 4096 kbps. The clock rates can range from 256 kHz to
8196 kHz. Under HWC mode, the number of bytes per frame is limited to 32.
The input and output data from the TSI are connected to the codec CDATI and CDATO pins for the
appropriate time slot. The CDATO pin is tri-stated except during programmed time slots. Only
twelve (12) codecs are supported in the MPC mode.
The LXP730 is always the master on the codec bus. The LXP730 can be configured to derive the
clock and frame pulse from either MCLK (in codec Master mode) or from the DSL clock using the
internal ADPLL (in codec Slave mode). One LXP730 of the DSL link must be in the Master codec
mode and the other in the Slave codec mode.
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