
Multi-Rate DSL Framer
—
LXP730
Datasheet
25
The Z bits may either accessed through the registers or the OSIO interface. This is controlled by the
Z_CTL bit in register 23h, MISC_CTL. When OH and Z bits both go through the OSIO, they go in
order as listed in the frame structure in
Table 7
. For example: if transparent OH and Z bits all go
through the OSIO, then the order for an MDSL frame is 2 OH bits, 12 Z bits, 10 OH bits, 12 Z bits,
10 OH bits, 12 Z bits, 10 OH bits, 12 Z bits. Switching to OH predefined, the corresponding
predefined OH bits would not appear at the OSIO and there would be a gap at those time locations.
In HWC mode all the Z bits and the user definable OH bits go through the OSIO.
When the LXP730 is in fractional T1 mode, Z bits are part of the payload and not accessible,
otherwise they are accessible in the Z bit registers.
2.13
MDSL Frame Format
The LXP730 has a transport frame format that adjusts automatically with the
N
setting. The overall
structure remains constant while adjusting the number of time slots within the payload blocks.
Table 7
and
Figure 4
shows the overall frame format.
The frame is made up of a sync word, followed by alternating sets of MDSL Overhead bits and
groups of data blocks. The final element of each frame is a section set aside for stuffing, used to
synchronize payload with DSL framing where required.
Table 6. MDSL Frame Sync Word (FSW) Patterns
Type Pattern
Bits
Quat Value
Normal
10101000001000
+3 +3 +3 -3 -3 +3 -3
Time-reversed
00100000101010
-3 +3 -3 -3 +3 +3 +3
Inverted-Sign-Bit
00000010100010
-3 -3 -3 +3 +3 -3 +3
Inverted-Sign-Time-Reversed
10001010000000
+3 -3 +3 +3 -3 -3 -3
Table 7. MDSL Frame Format
Description
Number of Bits
Sync Word
14
MOH
2
B1-B12
[
Z
+ (N
×
8)]
×
12
MOH
10
B13-B24
[
Z
+ (N
×
8)]
×
12
MOH
10
B25-B36
[
Z
+ (N
×
8)]
×
12
MOH
10
B37-B48
[
Z
+ (N
×
8)]
×
12
Stuff
0 or 4, typ avg 2