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參數(shù)資料
| 型號(hào)： | LUCW3000CCN |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
| 封裝： | TSSOP-14 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 326K |
| 代理商： | LUCW3000CCN |
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Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Lucent Technologies Inc.
13
REF Register (continued)
Table 13. D5: Phase Detector Polarity (Bit 17)
D5
Phase Detector Polarity
0
Negative slope
1
Positive slope
The phase detector can be programmed for either a negative or positive slope to accommodate the VCO and
low-pass filter characteristics. (See Figure 7.)
LOOP
FILTER
REFERENCE
W3000
VCO
OUTPUT
FREQUENCY
1
0
VCO INPUT CONTROL
VOLTAGE
Figure 7. Programming the Phase Detector Slope
Table 14. RE: Reset (Bit 20)
RE
Response
0
Operation mode
1
Reset MAIN and secondary registers
After the power supply is turned on, the REF register must be programmed with a reset. This must be followed by
a programming of the MAIN register before or at the enabling of the PLL circuit.
The RE bit will clear itself, and is required to ensure correct initialization of the IC. This results in the following
conditions:
+
The RE bit is cleared back to 0.
+
The device is in powerdown mode, since the EN[1:2] bits are also cleared.
+
Previous reference and main counter values are maintained.
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