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參數(shù)資料
| 型號： | LUCW3000CCN |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
| 封裝： | TSSOP-14 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 326K |
| 代理商： | LUCW3000CCN |
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Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Lucent Technologies Inc.
19
Application Information
A typical PLL system can be modeled as follows:
+
KPD
Z(s)
KVCO
1/N
fREF
1/R
s
fVCO
Figure 11. Typical PLL Model
KPD
= Phase detector in mA/2
π rad
Z(s) = Loop filter
KVCO = VCO gain in MHz/V
N
= Total divide ratio
R
= Reference divide ratio
Where the open loop gain is:
G(s)OPEN =
Ns
Kvco
*
)
s
(
Z
*
KPD
Where
s = j
ω
The circuit shown in Figure 12 uses a passive third-order loop filter for the element Z(s), defined by the network:
C1
R1
C3
R2
C2
CHARGE PUMP
OUTPUT
VCO
Figure 12. Third-Order Loop Filter
The purpose of the loop filter is to provide response with bandwidth sufficient not only to allow a quick lock time
but also to meet phase-noise and reference sideband requirements. Addition of a third pole formed by R2 and C3
will improve reference sideband performance with little overall impact on the loop performance. A reasonable
practical limit is that the f comparison is greater than 5 times loop bandwidth.
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