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參數(shù)資料
| 型號： | LUCW3000CCN |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO14 |
| 封裝： | TSSOP-14 |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 326K |
| 代理商： | LUCW3000CCN |
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Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Lucent Technologies Inc.
11
REF Register
This section describes each bit of the reference register. The REF register is used for programming the division
ratio of the reference clock and for initial setup of the operation modes.
Table 7. REF Register Bit Description (C0 = 1, C1 = 0)
Bit
Name
Description
1
C0 = 1
Register address bit. C0 = 1 for REF (last bit in serial sequence).
2:12
R[1:11]
Reference frequency divide ratio.
13
D1
Forced counter reload programming (synchronous/asynchronous).
14
D2
Charge pump disable function.
15:16
D3, D4
Programable charge pump current for frequency band 2.
17
D5
Phase detector polarity.
18:19
D6, D7
Programable charge pump current for frequency band 1.
20
RE
Reset for first programming after powerup (1 = reset).
21
ERES
Enables external resistor (on RES pin) to set charge pump current.
22
EN1
Enable W3000. (0 is powerdown.)
23
LD
Lock detect output enable.
24
C1 = 0
Secondary address bit (first bit in serial sequence).
Table 8. REF Register
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C0
= 1
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
D
1
D
2
D
3
D
4
D
5
D
6
D
7
RE ERES EN LD
C1
= 0
Table 9. R1:R11: Reference Divider Ratio (Bits 2 to 12)
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
Divide Ratio R
—
—*
0
1
0
2
0
1
3
.
1
2047
*The reference counter cannot operate with division numbers less than 2.
Last bit in serial sequence
First bit in serial sequence
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