參數(shù)資料
型號: LTC3831IGN
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù): 4/20頁
文件大?。?/td> 208K
代理商: LTC3831IGN
LTC3831
12
3831fb
APPLICATIONS INFORMATION
than 7V, a 12V zener diode should be included from PVCC1
to PGND to prevent transients from damaging the circuitry
at PVCC1 or the gate of Q1.
For applications with a lower VIN supply, a tripling charge
pump circuit shown in Figure 7 can be used to provide
2VIN and 3VIN gate drive for the external top and bottom
MOSFETs respectively. This circuit provides 3VIN – 3VF to
PVCC1 while Q1 is ON and 2VIN – 2VF to PVCC2 where VF
is the forward voltage of the Schottky diode. The circuit
requires the use of Schottky diodes to minimize forward
drop across the diodes at start-up. The tripling charge
pump circuit can rectify any ringing at the drain of Q2 and
provide more than 3VIN at PVCC1; a 12V zener diode should
be included from PVCC1 to PGND to prevent transients from
damaging the circuitry at PVCC1 or the gate of Q1.
The charge pump capacitors for PVCC1 refresh when the
BG pin goes high and the switch node is pulled low by
Q2. The BG on time becomes narrow when the LTC3831
operates at maximum duty cycle (95% typical) which
can occur if the input supply rises more slowly than the
soft-start capacitor or the input voltage droops during
load transients. If the BG on time gets so narrow that the
switch node fails to pull completely to ground, the charge
pump voltage may collapse or fail to start causing excessive
dissipation in external MOSFET Q1. This is most likely with
low VCC voltages and high switching frequencies, coupled
with large external MOSFETs that slow the BG and switch
node slew rates.
The LTC3831 overcomes this problem by sensing the
PVCC1 voltage when TG is high. If PVCC1 is less than 2.5V
above VCC, the maximum TG duty cycle is reduced to
70% by clamping the COMP pin at 1.8V (QC in the Block
Diagram). This increases the BG on time and allows the
charge pump capacitors to be refreshed.
For applications using an external supply to power PVCC1,
this supply must also be higher than VCC by at least 2.5V
to ensure normal operation.
Connecting the Ratiometric Reference Input
The LTC3831 derives its ratiometric reference, VREF,
using an internal resistor divider. The top and bottom of
the resistor divider is connected to the R+ and Rpins
respectively. This permits the output voltage to track at
a ratio of the differential voltage at R+ and R.
The LTC3831 can operate with a minimum VFB of 1.1V
and maximum VFB of (VCC – 1.75V). With Rconnected
to GND, this gives a VR+ input range of 2.2V to (2 VCC
– 3.5V). If VR+ is higher than the permitted input voltage,
increase the VCC voltage to raise the input range.
In a typical DDR memory termination application as shown
in Figure 1, R+ is connected to VDDQ, the supply voltage
of the interface, and Rto GND. The output voltage VTT is
connected to the FB pin, so VTT = 0.5 VDDQ.
If a ratio greater than 0.5 is desired, it can be achieved
using an external resistor divider connected to VTT and
FB pin. Figure 8 shows an application that generates a
VTT of 0.6 VDDQ.
Figure 7. Tripling Charge Pump
LTC3831
3831 F07
+
DZ
12V
1N5242
10μF
TG
BG
0.1μF
Q1
LO
Q2
COUT
VOUT
0.1μF
PVCC2
1N5817
PVCC1
VIN
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