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參數(shù)資料
| 型號(hào)： | LTC2442CG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er |
| 中文描述： | 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO36 |
| 封裝： | 5.30 MM, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 392K |
| 代理商： | LTC2442CG |
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LTC2442
7
2442f
PIU
SCK (Pin 1):
Bidirectional Digital Clock Pin. In internal serial
clock operation mode, SCK is used as a digital output for
the internal serial interface clock during the data output
period. In the external serial clock operation mode, SCK
is used as the digital input for the external serial interface
clock during the data output period. The serial clock op-
eration mode is determined by the logic level applied to
EXT (Pin 3).
BUSY (Pin 2):
Conversion in Progress Indicator. This pin
is HIGH while the conversion is in progress and goes LOW
indicating the conversion is complete and data is ready.
It remains LOW during the sleep and data output states.
At the conclusion of the data output state, it goes HIGH
indicating a new conversion has begun.
EXT (Pin 3):
Internal/External SCK Selection Pin. This
pin is used to select internal or external SCK for output-
ting/inputting data. If EXT is tied low, the device is in the
external SCK mode and data is shifted out of the device
under the control of a user applied serial clock. If EXT is
tied high, the internal serial clock mode is selected. The
device generates its own SCK signal and outputs this on
the SCK pin. A framing signal BUSY (Pin 2) goes low
indicating data is being output.
GND (Pins 4, 5, 32):
Ground. Multiple ground pins inter-
nally connected for optimum ground current flow and V
CC
decoupling. Connect each one of these pins to a common
ground plane through a low impedance connection. All three
pins must be connected to ground for proper operation.
CH0 to CH3 (Pins 6, 7, 8, 9):
Analog Inputs. May be
programmed for single-ended or differential mode. (See
Table 3)
ANCINB (Pin 10):
ADC Input. Must tie to the amplifier
output, OUTB (Pin 17).
ADCINA (Pin 11):
ADC Input. Must tie to the amplifier
output, OUTA (Pin 12).
OUTA (Pin 12):
Amplifier A output. Must be compensated
with 0.1μF or greater capacitor. Drives the ADCINA ADC
input (Pin 11).
–INA (Pin 13):
Amplifier A negative Input. By shorting this
pin to OUTA (Pin 12) the amplifier becomes a buffer with
unity gain. Alternatively, an external resistor network may
be added here for gains greater than 1.
NC (Pins 14, 15, 16, 20, 22, 23):
No Connect. These pins
should be left floating or tied to Ground.
OUTB (Pin 17):
Amplifier B Output. Must be compensated
with 0.1μF or greater capacitor. Drives the ADCINB ADC
input (Pin 10).
–INB (Pin 18):
Amplifier B negative Input. By shorting this
pin to OUTB (Pin 17) the amplifier becomes a buffer with
unity gain. Alternatively, an external resistor network may
be added here for gains greater than 1.
+INB (Pin 19):
Amplifier B positive Input. Must tie to the
Multiplexer output MUXOUTB (Pin 26).
V
+
(Pin 21):
Amplifier positive supply voltage input. May
tie to V
CC
or an external supply voltage up to 15V. Bypass
to GND with 1μF capacitor.
V
–
(Pin 24):
Amplifier Negative supply voltage input. May
tie to GND or an external supply voltage as low as –15V.
Bypass to GND with a 1μF capacitor.
+INA (Pin 25):
Amplifier A positive Input. Must tie to the
Multiplexer output MUXOUTA (Pin 27).
MUXOUTB (Pin 26):
Multiplexer Output. Must tie to +INB
amplifier input (Pin 19).
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