參數(shù)資料
型號(hào)： LTC2442CG
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er
中文描述： 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO36
封裝： 5.30 MM, PLASTIC, SSOP-36
文件頁(yè)數(shù)： 16/32頁(yè)
文件大?。?/td> 392K
代理商： LTC2442CG
LTC2442
16
2442f
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and control
the state of the conversion cycle, see Figure 4.
The serial clock mode is selected by the EXT pin. To select
the external serial clock mode, EXT must be tied low.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 (BUSY = 1) while a conversion is in progress
and EOC = 0 (BUSY = 0) if the device is in the sleep state.
Independent of CS, the device automatically enters the
sleep state once the conversion is complete.
When the device is in the sleep state (EOC = 0), its conver-
sion result is held in an internal static shift register. The
device remains in the sleep state until the first rising edge
of SCK is seen. Data is shifted out the SDO pin on each
falling edge of SCK. This enables external circuitry to latch
the output on the rising edge of SCK. EOC can be latched
on the first rising edge of SCK and the last bit of the con-
version result can be latched on the 32nd rising edge of
SCK. On the 32nd falling edge of SCK, the device begins
a new conversion. SDO goes HIGH (EOC = 1) and BUSY
goes HIGH indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
APPLICATIU
W
U
U
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
BIT 20 BIT 19
BIT 0
LSB
Hi-Z
2442 F04
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
BIT 31
1
0
EN
SGL
0
0
A0
OSR3
OSR2
OSR1
OSR0
TWOX
ODD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
TEST EOC
TEST EOC
V
CC
V
+
+INA
MUXOUTA
BUSY
SDO
SDI
EXT
SCK
F
O
MUXOUTB
+INB
GND
21
6
7
8
9
28
12
13
11
17
18
10
26
25
4, 5, 32
19
27
2
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
24
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
1
μ
F
0.1
μ
F
4.5V TO 5.5V
V
CC
TO 15V
LTC2442
1
μ
F
0.1
μ
F
CS
4-WIRE
SPI INTERFACE
–15V TO GND
V
–
REF
+
REF
–
OUTB
–INB
ADCINB
OUTA
–INA
ADCINA
CH0
CH1
CH2
CH3
COM
29
30
31
3
33
1
36
35
Figure 4. External Serial Clock, Single Cycle Operation
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