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參數(shù)資料
| 型號： | LTC2442CG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er |
| 中文描述： | 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO36 |
| 封裝： | 5.30 MM, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 392K |
| 代理商： | LTC2442CG |
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LTC2442
15
2442f
selected speed/resolution and input channel is valid. This
is identical to the operation of the LTC2440 and LTC2444
through LTC2449.
While operating in the 2X mode, the device performs a
running average of the last two conversion results. This
automatically removes the offset and drift of the device
while increasing the output rate by 2X. The resolution
(noise) remains the same. If a new channel is selected,
the conversion result is valid for all conversions after the
first conversion (one cycle latency). If a new speed/resolu-
tion is selected, the first conversion result is valid but the
resolution (noise) is a function of the running average.
All subsequent conversion results are valid. If the mode
is changed from either 1X to 2X or 2X to 1X without
changing the resolution or channel, the first conversion
result is valid.
The 2X mode can also be used to increase the settling
time of the amplifier between readings. While operating
in the 2X mode, the multiplexer output (input to the buf-
fer/amplifier) is switched at the end of each conversion
cycle. Prior to concluding the data out/in cycle, the analog
multiplexer output is switched. This occurs at the end of
the conversion cycle (just prior to the data output cycle)
for auto calibration. The time required to read the con-
version enables more settling time for the amplifier. The
offset/offset drift of the amplifier is automatically removed
by the converter’s auto calibration sequence for both the
1X and 2X speed modes.
While operating in the 1X mode, if a new input channel
is selected the multiplexer is switched on the falling edge
of the 14th SCK (once the complete data input word is
programmed). The remaining data output sequence time
can be used to allow the external amplifier to settle.
BUSY
The BUSY output (Pin 2) is used to monitor the state of
conversion, data output and sleep cycle. While the part is
converting, the BUSY pin is HIGH. Once the conversion
is complete, BUSY goes LOW indicating the conversion
is complete and data out is ready. The part now enters the
sleep state. BUSY remains LOW while data is shifted out of
the device and SDI is shifted into the device. It goes HIGH
at the conclusion of the data input/output cycle indicating
a new conversion has begun. This rising edge may be used
to flag the completion of the data read cycle.
Serial Interface Timing Modes
The LTC2442’s 3- or 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock, 3-
or 4-wire I/O, single cycle conversion and autostart. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (F
O
= LOW) or an external
oscillator connected to the F
O
pin. Refer to Table 5 for a
summary.
APPLICATIU
W
U
U
Table 5. Interface Timing Modes
Configuration
External SCK, Single Cycle Conversion
External SCK, 2-Wire I/O
Internal SCK, Single Cycle Conversion
Internal SCK, 2-Wire I/O, Continuous
Conversion
SCK Source
External
External
Internal
Internal
Conversion Cycle Control
CS and SCK
SCK
CS
↓
Continuous
Data Output Control
CS and SCK
SCK
CS
↓
Internal
Connection and Waveforms
Figures 4, 5
Figure 6
Figures 7, 8
Figure 9
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