參數(shù)資料
型號(hào)： LTC2442CG
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er
中文描述： 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO36
封裝： 5.30 MM, PLASTIC, SSOP-36
文件頁數(shù)： 21/32頁
文件大?。?/td> 392K
代理商： LTC2442CG
LTC2442
21
2442f
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion
This timing mode uses a 3-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 9. CS may be permanently tied to ground, simplifying
the user interface or isolation barrier. The internal serial
clock mode is selected by tying EXT HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW
(EOC = 0) indicating the conversion has finished and the
APPLICATIU
W
U
U
device has entered the sleep state. The part remains in
the sleep state a minimum amount of time (≈500ns) then
immediately begins outputting data. The data output cycle
begins on the first rising edge of SCK and ends after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
CS
SCK
SDI
SDO
BUSY
2442 F09
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
BIT 20 BIT 19
BIT 0
SIG
BIT 29
“0”
BIT 30
EOC
BIT 31
1
0
EN
SGL
0
0
A0
OSR3
OSR2
OSR1
OSR0
TWOX
ODD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
DON'T CARE
DON'T CARE
V
CC
V
+
+INA
MUXOUTA
BUSY
SDO
SDI
EXT
SCK
F
O
MUXOUTB
+INB
GND
21
6
7
8
9
28
12
13
11
17
18
10
26
25
4, 5, 32
19
27
2
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
24
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
1
μ
F
0.1
μ
F
4.5V TO 5.5V
V
CC
TO 15V
LTC2442
1
μ
F
0.1
μ
F
CS
–15V TO GND
V
–
REF
+
REF
–
OUTB
–INB
ADCINB
CH0
CH1
CH2
CH3
COM
29
30
31
3
33
1
36
35
OUTA
–INA
ADCINA
3-WIRE
SPI INTERFACE
V
CC
Figure 9. Internal Serial Clock, Continuous Operation
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PDF描述
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