參數(shù)資料
型號: LPC2923FBD100
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁數(shù): 15/84頁
文件大?。?/td> 551K
代理商: LPC2923FBD100
LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
15 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
found in the specific subsystem description. Some branch clocks have special protection
since they clock vital system parts of the device and should not be switched off. See
Section 6.15.5
for more details of how to control the individual branch clocks.
Table 7.
Base clock
Base clock and branch clock overview
Branch clock name
Parts of the device clocked
by this branch clock
watchdog timer
ARM968E-S and TCMs
AHB bus infrastructure
AHB side of bridge in PCRSS
Flash Memory Controller
Embedded SRAM Controller 0
(16 kB)
Embedded SRAM Controller 1
(16 kB) (LPC2925 only)
General Subsystem
Vectored Interrupt Controller
Peripheral Subsystem
GPIO bank 0
GPIO bank 1
GPIO bank 5
Remark
BASE_SAFE_CLK
BASE_SYS_CLK
CLK_SAFE
CLK_SYS_CPU
CLK_SYS_SYS
CLK_SYS_PCRSS
CLK_SYS_FMC
CLK_SYS_RAM0
[1]
CLK_SYS_RAM1
CLK_SYS_GESS
CLK_SYS_VIC
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO5
[2]
[3]
CLK_SYS_IVNSS_A
CLK_SYS_MSCSS_A
CLK_SYS_DMA
CLK_SYS_USB
CLK_PCR_SLOW
AHB side of bridge of IVNSS
AHB side of bridge of MSCSS
GPDMA
USB registers
PCRSS, CGU, RGU and PMU
logic clock
APB side of the IVNSS
CAN controller Acceptance
Filter
CAN channel 0
CAN channel 1
I
2
C0
I
2
C1
LIN channel 0
LIN channel 1
BASE_PCR_CLK
[1]
[4]
BASE_IVNSS_CLK
CLK_IVNSS_APB
CLK_IVNSS_CANCA
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_I2C0
CLK_IVNSS_I2C1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
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