參數(shù)資料
型號: LPC2366FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: ARM7 with 256 kB flash, 58 kB SRAM, Ethernet, USB 2.0 Device, CAN, and 10-bit ADC
封裝: LPC2366FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁數(shù): 7/18頁
文件大?。?/td> 220K
代理商: LPC2366FBD100
ES_LPC2366
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 20 April 2011
7 of 18
NXP Semiconductors
ES_LPC2366
Errata sheet LPC2366
OLD_EMAC_MODULE_ID, P1.6 should not be set. */
PINSEL2 = 0x50150105;
/* selects P1[0,1,4,8,9,10,14,15] */
}
PINSEL3 = 0x00000005;
/* selects P1[17:16] */
3.4 Ethernet.2: Ethernet SRAM disabled
Introduction:
The LPC2366 has an Ethernet interface, which has a dedicated 16 kB SRAM.
Problem:
When the Ethernet block is disabled (in the PCONP register located at 0xE01F C0C4), the
Ethernet SRAM is also disabled.
Work-around:
Enable the Ethernet block by setting the PCENET bit (bit no. 30) in the PCONP register.
The Ethernet SRAM is now enabled.
3.5 Ethernet.3: Receive Status registers will not function correctly if
RxDescriptor number is greater than 4
Introduction:
The Receive number of Descriptors register (RxDescriptor-0xFFE0 0110) defines the
number of descriptors in the Descriptor array. Each receive descriptor element in the
Descriptor array has an associated status field which consists of the HashCRC word and
Status Information word.
Problem:
The status words are updated incorrectly if the number of Descriptors set in the Receive
number of Descriptors register is greater than or equal to 5.
Work-around:
Define 4 or less in the Receive number of Descriptors register.
3.6 I2S.1: I
2
S DMA interface is non-operational
Introduction:
The LPC2366 has an I
2
S interface, which can be used for audio devices. The I
2
S interface
was initially designed to operate with the general purpose DMA controller.
Problem:
The DMA controller cannot access the I
2
S interface.
Work-around:
No known workaround.
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