參數(shù)資料
型號: LPC2366FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: ARM7 with 256 kB flash, 58 kB SRAM, Ethernet, USB 2.0 Device, CAN, and 10-bit ADC
封裝: LPC2366FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁數(shù): 5/18頁
文件大?。?/td> 220K
代理商: LPC2366FBD100
ES_LPC2366
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 20 April 2011
5 of 18
NXP Semiconductors
ES_LPC2366
Errata sheet LPC2366
3. Functional problems detail
3.1 Ethernet.4: Ethernet TxConsumeIndex register does not update
correctly after the first frame is sent
Introduction:
The transmit consume index register defines the descriptor that is going to be transmitted
next by the hardware transmit process. After a frame has been transmitted hardware
increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has
been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is
empty and the transmit channel will stop transmitting until software produces new
descriptors.
Problem:
The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is
sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to
2). This only happens the very first time, so subsequent updates are correct (even those
from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been
reached)
Work-around:
Software can correct this situation in many ways; for example, sending a dummy frame
after initialization.
3.2 ADC.1: ADDRx read conflicts with hardware setting of the DONE bit
Introduction:
The LPC2366 has a 10-bit ADC, which can be used to measure analog signals and
convert the signals into a 10-bit digital result. There are eight A/D channels and each
channel has its own individual A/D Data Register (ADDR0 to ADDR7). The A/D Data
Register holds the result when an A/D conversion is complete, and also includes the flags
that indicate when a conversion has been completed (DONE bit) and when a conversion
overrun has occurred. The DONE bit is cleared when the respective A/D Data Register is
read.
Problem:
If a software read of ADDRx conflicts with the hardware setting of the DONE bit in the
same register (once a conversion is completed) then the DONE bit gets cleared
automatically, thereby clearing the indication that a conversion was completed.
Work-around:
For software controlled mode or burst mode with only one channel selected, the DONE bit
in the A/D Global Data Register (located at 0xE003 4004) can be used instead of the
individual ADDRx result register with no impact on performance.
For burst mode with multiple channels selected, the DONE bit together with the CHN field
in the A/D Global Data Register can be used with some impact on throughput.
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