參數(shù)資料
型號(hào): LPC2366FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: ARM7 with 256 kB flash, 58 kB SRAM, Ethernet, USB 2.0 Device, CAN, and 10-bit ADC
封裝: LPC2366FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁數(shù): 3/18頁
文件大?。?/td> 220K
代理商: LPC2366FBD100
ES_LPC2366
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 20 April 2011
3 of 18
NXP Semiconductors
ES_LPC2366
Errata sheet LPC2366
1. Product identification
The LPC2366 devices typically have the following top-side marking:
LPC2366xxx
xxxxxxx
xxYYWWR[x]
The last/second to last letter in the third line (field ‘R’) will identify the device revision. This
Errata Sheet covers the following revisions of the LPC2366:
Table 1.
Revision identifier (R)
‘-’
‘A’
‘B’
‘D’
Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the
device was manufactured during that year.
2. Errata overview
Device revision table
Revision description
Initial device revision
Second device revision
Third device revision
Fourth device revision
Table 2.
Functional
problems
Ethernet.4
Functional problems table
Short description
Revision identifier
Detailed description
Ethernet TxConsumeIndex register does not update
correctly after the first frame is sent
ADDRx read conflicts with hardware setting of DONE
bit
Setting up the Ethernet interface in RMII mode
Ethernet SRAM disabled
RxDescriptor number cannot be greater than 4
I
2
S DMA can stall
PLL output is limited to 290 MHz
16 kB SRAM can not be used for code execution
USB_NEED_CLK is always asserted
U1CONNECT is not functional
V
BUS
status input is not functional
Accessing non-Watchdog APB registers in the middle
of the feed sequence causes a reset
Incorrect update of the Abort Link register in Thumb
state
Operating speed out of on-chip flash is restricted
Code execution failure can occur with MAM Mode 2
Data overrun condition can lock the CAN controller
‘-’, ‘A’, ‘B’, ‘D’
Section 3.1 on page 5
ADC.1
‘-’
Section 3.2 on page 5
Ethernet.1
Ethernet.2
Ethernet.3
I2S.1
PLL.1
SRAM.1
USB.1
USB.2
USB.3
WDT.1
‘-’
‘-’
‘-’
‘-’
‘-’
‘-’
‘-’
‘-’
‘-’
‘-’
Section 3.3 on page 6
Section 3.4 on page 7
Section 3.5 on page 7
Section 3.6 on page 7
Section 3.7 on page 8
Section 3.8 on page 8
Section 3.9 on page 9
Section 3.10 on page 9
Section 3.11 on page 9
Section 3.12 on page 10
Core.1
‘-’, ‘A’, ‘B’, ‘D’
Section 3.13 on page 10
Flash.1
MAM.1
CAN.1
‘-’, ‘A’
‘-’, ‘A’
‘-’, ‘A’, ‘B’
Section 3.14 on page 11
Section 3.15 on page 12
Section 3.16 on page 12
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