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參數(shù)資料
| 型號(hào)： | LMX2512LQX0967/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 19.68 MHz, QCC28 |
| 封裝： | 5 X 5 MM, 0.75 MM HEIGHT, LLP-28 |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大小： | 184K |
| 代理商： | LMX2512LQX0967/NOPB |
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Programming Description (Continued)
R3 REGISTER
The R3 register address bits (R3 [2:0]) are “011”.
Register R3 contains the controls for the phase lock bandwidth controls (BW_DUR, BW_CRL, and BW_EN). The duration of the
digital controller portion of the bandwidth control is set by BW_DUR [1:0]. The minimum time set with 00 and increasing durations
to the maximum value set with 11. BW_CRL [1:0] sets the phase offset criterion for the bandwidth controller. Once the phase
offset between the reference clock and the divided VCO signal are within the set criterion, the bandwidth control stops. The
maximum phase offset is set with 00 and decreases to the minimum value set with 11. BW_EN enables the bandwidth control in
the locking state.
The VCO dynamic current is also controlled in register R3 with VCO_CUR [1:0]. The minimum value corresponds to 00 and
increases to a maximum value set at 11.
R3 REGISTER
Register
MSB
SHIFT REGISTER BIT LOCATION
LSB
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987654
3
210
Data Field
Address
Field
R3
(Default)
BW_
DUR
[1:0]
BW_
CRL
[1:0]
BW_
EN
10111101
0
00110
VCO_
CUR
[1:0]
011
Name
Functions
BW_DUR [1:0]
Bandwidth Duration
00 = Minimum value (Recommended)
01 =
10 =
11 = Maximum value
BW_CRL [1:0]
Bandwidth Control
00 = Maximum phase offset (Recommended)
01 =
10 =
11 = Minimum phase offset
BW_EN
Bandwidth Enable
0 = Disable
1 = Enable (Recommended)
VCO_CUR [1:0]
VCO Dynamic Current
00 = Minimum value
01 =
10 =
11 = Maximum value (Recommended)
LMX2502/LMX2512
www.national.com
15
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