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參數(shù)資料
| 型號： | LMX2512LQX0967/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 19.68 MHz, QCC28 |
| 封裝： | 5 X 5 MM, 0.75 MM HEIGHT, LLP-28 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 184K |
| 代理商： | LMX2512LQX0967/NOPB |
Programming Description (Continued)
R0 REGISTER
The R0 register address bits (R0 [1:0]) are “00”.
The SPI_DEF bit selects between using the default IF counter values and user programmable values. The use of the default
counter values requires that only words R0 to R3 (registers R3, loaded first, to R0, loaded last) be sent after initial power up.
The RF_LD bit activates the lock detect output of the LD pin (pin 19). The lock detect mode shows the lock status of the RF PLL.
The waveform of the lock detect mode is shown in Figure 1,inthe Functional Description section on LOCK DETECT.
The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the
11-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values are presented below.
R0 REGISTER
Register
MSB
SHIFT REGISTER BIT LOCATION
LSB
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987654321
0
Data Field
Address
Field
R0
(Default)
SPI_
DEF
RF_
SEL
RF_
LD
0
RF_B
[3:0]
RF_A
[2:0]
RF_FN
[10:0]
00
Name
Functions
SPI_DEF
Default Register Selection
0 = OFF (Use values set in R0 to R6)
1 = ON (Use default values set in R0 to R3)
RF_SEL
RF VCO Selection
0 = LMX2512
1 = LMX2502
RF_LD
RF Lock Detect
0 = Hard zero (GND)
1 = Lock detect
RF_B [3:0]
RF_B Counter
4-bit programmable counter
2
≤ RF_B ≤ 15
RF_A [2:0]
RF_A Counter
3-bit swallow counter
0
≤ RF_A ≤ 7 for LMX2502
0
≤ RF_A ≤ 5 for LMX2512
RF_FN [10:0]
RF Fractional Numerator Counter
11-bit programmable counter
0
≤ RF_FN < 1920 for f
OSC = 19.20 MHz
0
≤ RF_FN < 1968 for f
= 19.68 MHz
LMX2502/LMX2512
www.national.com
11
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