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參數(shù)資料
| 型號(hào)： | LMX2512LQX0967/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 19.68 MHz, QCC28 |
| 封裝： | 5 X 5 MM, 0.75 MM HEIGHT, LLP-28 |
| 文件頁(yè)數(shù)： | 17/18頁(yè) |
| 文件大小： | 184K |
| 代理商： | LMX2512LQX0967/NOPB |
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Functional Description (Continued)
TABLE 2. Power Down Configuration
CE Pin
RF_EN
IF_EN
RF Circuitry
IF Circuitry
0
X
OFF
1
0
OFF
1
0
1
OFF
ON
1
0
ON
OFF
11
1
ON
X = Don’t care.
LOCK DETECT
The LD output can be used to indicate the lock status of the
RF PLL. Bit 21 in Register R0 determines the signal that
appears on the LD pin. When the RF PLL is not locked, the
LD pin remains LOW. After obtaining phase lock, the LD pin
will have a logical HIGH level. The output can also be
programmed to be ground at all times.
TABLE 3. Lock Detect Modes
LD Bit
Mode
0
Disable (GND)
1
Enable
TABLE 4. Lock Detect Logic
RF PLL Section
LD Output
Locked
HIGH
Not Locked
LOW
Note 9: LD output becomes LOW when the phase error is larger than tW2.
Note 10: LD output becomes HIGH when the phase error is less than tW1 for
four or more consecutive cycles.
Note 11: Phase Error is measured on leading edge. Only errors greater than
tW1 and tW2 are labeled.
Note 12: tW1 and tW2 are equal to 10 ns.
Note 13: The lock detect comparison occurs with every 64th cycle of fR and
fN.
20068005
FIGURE 1. Lock Detect Timing Diagram Waveform (Notes 9, 10, 11, 12, 13)
LMX2502/LMX2512
www.national.com
8
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